betsy: preliminary beta snapshot

1 files changed, 105 insertions, 0 deletions

diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v
new file mode 100644
index 0000000..f489c24
--- /dev/null
+++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v
@@ -0,0 +1,105 @@
+// megafunction wizard: %ALTDDIO_BIDIR%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTDDIO_BIDIR 
+
+// ============================================================
+// File Name: ddrio.v
+// Megafunction Name(s):
+// 			ALTDDIO_BIDIR
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition
+// ************************************************************
+
+//Copyright (C) 2025  Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Altera and sold by Altera or its authorized distributors.  Please
+//refer to the Altera Software License Subscription Agreements 
+//on the Quartus Prime software download page.
+
+module ddrio (
+	aclr,
+	datain_h,
+	datain_l,
+	inclock,
+	inclocken,
+	oe,
+	outclock,
+	outclocken,
+	dataout_h,
+	dataout_l,
+	padio);
+
+	input	  aclr;
+	input	[7:0]  datain_h;
+	input	[7:0]  datain_l;
+	input	  inclock;
+	input	  inclocken;
+	input	  oe;
+	input	  outclock;
+	input	  outclocken;
+	output	[7:0]  dataout_h;
+	output	[7:0]  dataout_l;
+	inout	[7:0]  padio;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON"
+// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
+// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
+// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]"
+// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0
+// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]"
+// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0
+// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]"
+// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0
+// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]"
+// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken"
+// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0
+// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
+// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken"
+// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0
+// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]"
+// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE