diff options
| author | mindchasers <privateisland@mindchasers.com> | 2020-09-27 20:54:08 -0400 |
|---|---|---|
| committer | mindchasers <privateisland@mindchasers.com> | 2020-09-27 20:54:08 -0400 |
| commit | 1c7478194daae4be777a21552295133a735082cb (patch) | |
| tree | e55d68f643b4b5ab375fe3942728dc931c8ef1ad /clarity/pcs | |
| parent | bbe7e48ee202c2e1075ea6a69733d030b8bf3ddf (diff) | |
clarity: update SERDES/PCS block to be compatible with Diamond 3.11
Diffstat (limited to 'clarity/pcs')
| -rw-r--r-- | clarity/pcs/pcs.sbx | 96 | ||||
| -rw-r--r-- | clarity/pcs/pcs.v | 8 | ||||
| -rw-r--r-- | clarity/pcs/pcs_tmpl.v | 46 | ||||
| -rw-r--r-- | clarity/pcs/refclk0/refclk0.lpc | 4 | ||||
| -rw-r--r-- | clarity/pcs/refclk0/refclk0.v | 2 | ||||
| -rw-r--r-- | clarity/pcs/sgmii0/sgmii0.fdc | 3 | ||||
| -rw-r--r-- | clarity/pcs/sgmii0/sgmii0.lpc | 12 | ||||
| -rw-r--r-- | clarity/pcs/sgmii0/sgmii0.v | 102 | ||||
| -rw-r--r-- | clarity/pcs/sgmii1/sgmii1.fdc | 3 | ||||
| -rw-r--r-- | clarity/pcs/sgmii1/sgmii1.lpc | 12 | ||||
| -rw-r--r-- | clarity/pcs/sgmii1/sgmii1.v | 94 | ||||
| -rw-r--r-- | clarity/pcs/sgmii2/sgmii2.fdc | 3 | ||||
| -rw-r--r-- | clarity/pcs/sgmii2/sgmii2.lpc | 12 | ||||
| -rw-r--r-- | clarity/pcs/sgmii2/sgmii2.v | 104 | ||||
| -rw-r--r-- | clarity/pcs/sgmii3/sgmii3.fdc | 3 | ||||
| -rw-r--r-- | clarity/pcs/sgmii3/sgmii3.lpc | 12 | ||||
| -rw-r--r-- | clarity/pcs/sgmii3/sgmii3.v | 94 |
17 files changed, 317 insertions, 293 deletions
diff --git a/clarity/pcs/pcs.sbx b/clarity/pcs/pcs.sbx index 6941e9c..d36bdc1 100644 --- a/clarity/pcs/pcs.sbx +++ b/clarity/pcs/pcs.sbx @@ -2033,8 +2033,8 @@ <lattice:device>LFE5UM-45F-8BG381C</lattice:device> <lattice:synthesis>synplify</lattice:synthesis> <lattice:date>2017-06-09.17:06:27</lattice:date> - <lattice:modified>2019-03-15.18:48:22</lattice:modified> - <lattice:diamond>3.10.3.144</lattice:diamond> + <lattice:modified>2020-03-21.21:49:34</lattice:modified> + <lattice:diamond>3.11.2.446</lattice:diamond> <lattice:language>Verilog</lattice:language> <lattice:attributes> <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> @@ -2143,7 +2143,7 @@ </spirit:model> <spirit:vendorExtensions> <lattice:synthesis>synplify</lattice:synthesis> - <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:modified>2020-03-21.21:49:34</lattice:modified> <lattice:attributes> <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> <lattice:attribute lattice:name="BBox">false</lattice:attribute> @@ -2222,7 +2222,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Date</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">10/17/2017</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">03/06/2020</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>ModuleName</lattice:lpckey> @@ -2238,7 +2238,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Time</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">18:21:09</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">20:20:44</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>VendorName</lattice:lpckey> @@ -2589,6 +2589,13 @@ </spirit:vendorExtensions> </spirit:port> <spirit:port> + <spirit:name>tx_full_clk</spirit:name> + <spirit:displayName>tx_full_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> <spirit:name>tx_pclk</spirit:name> <spirit:displayName>tx_pclk</spirit:displayName> <spirit:wire> @@ -2748,7 +2755,7 @@ </spirit:model> <spirit:vendorExtensions> <lattice:synthesis>synplify</lattice:synthesis> - <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:modified>2020-03-21.21:49:34</lattice:modified> <lattice:attributes> <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> <lattice:attribute lattice:name="BBox">false</lattice:attribute> @@ -2827,7 +2834,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Date</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">03/15/2019</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">03/21/2020</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>ModuleName</lattice:lpckey> @@ -2843,7 +2850,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Time</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">18:47:34</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">21:48:39</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>VendorName</lattice:lpckey> @@ -2880,11 +2887,11 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_MULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CH_MODE</lattice:lpckey> @@ -2956,7 +2963,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>REFCLK_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>RSTSEQSEL</lattice:lpckey> @@ -3100,7 +3107,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TXPLLMULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> @@ -3428,6 +3435,13 @@ </spirit:wire> </spirit:port> <spirit:port> + <spirit:name>tx_full_clk</spirit:name> + <spirit:displayName>tx_full_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> <spirit:name>tx_pclk</spirit:name> <spirit:displayName>tx_pclk</spirit:displayName> <spirit:wire> @@ -3587,7 +3601,7 @@ </spirit:model> <spirit:vendorExtensions> <lattice:synthesis>synplify</lattice:synthesis> - <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:modified>2020-03-21.21:49:34</lattice:modified> <lattice:attributes> <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> <lattice:attribute lattice:name="BBox">false</lattice:attribute> @@ -3666,7 +3680,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Date</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">11/18/2018</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">03/21/2020</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>ModuleName</lattice:lpckey> @@ -3682,7 +3696,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Time</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">17:42:50</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">21:47:13</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>VendorName</lattice:lpckey> @@ -3719,11 +3733,11 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_MULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CH_MODE</lattice:lpckey> @@ -3795,7 +3809,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>REFCLK_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>RSTSEQSEL</lattice:lpckey> @@ -3899,7 +3913,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>SOFTLOL</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TX8B10B</lattice:lpckey> @@ -3939,7 +3953,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TXPLLMULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> @@ -4294,6 +4308,13 @@ </spirit:vendorExtensions> </spirit:port> <spirit:port> + <spirit:name>tx_full_clk</spirit:name> + <spirit:displayName>tx_full_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> <spirit:name>tx_pclk</spirit:name> <spirit:displayName>tx_pclk</spirit:displayName> <spirit:wire> @@ -4453,7 +4474,7 @@ </spirit:model> <spirit:vendorExtensions> <lattice:synthesis>synplify</lattice:synthesis> - <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:modified>2020-03-21.21:49:34</lattice:modified> <lattice:attributes> <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> <lattice:attribute lattice:name="BBox">false</lattice:attribute> @@ -4532,7 +4553,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Date</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">03/15/2019</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">03/21/2020</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>ModuleName</lattice:lpckey> @@ -4548,7 +4569,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Time</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">18:46:19</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">21:49:06</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>VendorName</lattice:lpckey> @@ -4585,11 +4606,11 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_MULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CH_MODE</lattice:lpckey> @@ -4661,7 +4682,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>REFCLK_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>RSTSEQSEL</lattice:lpckey> @@ -4805,7 +4826,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TXPLLMULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> @@ -5133,6 +5154,13 @@ </spirit:wire> </spirit:port> <spirit:port> + <spirit:name>tx_full_clk</spirit:name> + <spirit:displayName>tx_full_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> <spirit:name>tx_pclk</spirit:name> <spirit:displayName>tx_pclk</spirit:displayName> <spirit:wire> @@ -5292,7 +5320,7 @@ </spirit:model> <spirit:vendorExtensions> <lattice:synthesis>synplify</lattice:synthesis> - <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:modified>2020-03-21.21:49:34</lattice:modified> <lattice:attributes> <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> <lattice:attribute lattice:name="BBox">false</lattice:attribute> @@ -5371,7 +5399,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Date</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">03/15/2019</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">03/21/2020</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>ModuleName</lattice:lpckey> @@ -5387,7 +5415,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>Time</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">18:46:48</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">21:49:26</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>VendorName</lattice:lpckey> @@ -5424,11 +5452,11 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_MULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>CH_MODE</lattice:lpckey> @@ -5500,7 +5528,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>REFCLK_RATE</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>RSTSEQSEL</lattice:lpckey> @@ -5644,7 +5672,7 @@ </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TXPLLMULT</lattice:lpckey> - <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue> </lattice:lpcentry> <lattice:lpcentry> <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> diff --git a/clarity/pcs/pcs.v b/clarity/pcs/pcs.v index 40bad95..8acba47 100644 --- a/clarity/pcs/pcs.v +++ b/clarity/pcs/pcs.v @@ -256,7 +256,7 @@ module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata, .signal_detect_c(sgmii0_signal_detect_c), .sli_rst(sli_rst_wire0), .tx_pclk(sgmii0_tx_pclk), .tx_pcs_rst_c(sgmii0_tx_pcs_rst_c), .tx_pwrup_c(sgmii0_tx_pwrup_c), .tx_serdes_rst_c(sgmii0_tx_serdes_rst_c), - .txi_clk(sgmii0_txi_clk)); + .txi_clk(sgmii0_txi_clk), .tx_full_clk()); sgmii1 sgmii1_inst (.rx_cv_err({sgmii1_rx_cv_err}), .rx_disp_err({sgmii1_rx_disp_err}), .rx_k({sgmii1_rx_k}), .rxdata({sgmii1_rxdata}), .sci_addr({sgmii0_sci_addr}), .sci_rddata({i_sgmii1_sci_rddata}), .sci_wrdata({sgmii0_sci_wrdata}), @@ -275,7 +275,7 @@ module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata, .serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii1_serdes_rst_dual_c), .signal_detect_c(sgmii1_signal_detect_c), .tx_pclk(sgmii1_tx_pclk), .tx_pcs_rst_c(sgmii1_tx_pcs_rst_c), .tx_pwrup_c(sgmii1_tx_pwrup_c), - .tx_serdes_rst_c(sgmii1_tx_serdes_rst_c), .txi_clk(sgmii1_txi_clk)); + .tx_serdes_rst_c(sgmii1_tx_serdes_rst_c), .txi_clk(sgmii1_txi_clk),.tx_full_clk()); sgmii2 sgmii2_inst (.rx_cv_err({sgmii2_rx_cv_err}), .rx_disp_err({sgmii2_rx_disp_err}), .rx_k({sgmii2_rx_k}), .rxdata({sgmii2_rxdata}), .sci_addr({sgmii2_sci_addr}), .sci_rddata({i_sgmii2_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}), @@ -295,7 +295,7 @@ module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata, .signal_detect_c(sgmii2_signal_detect_c), .sli_rst(sli_rst_wire2), .tx_pclk(sgmii2_tx_pclk), .tx_pcs_rst_c(sgmii2_tx_pcs_rst_c), .tx_pwrup_c(sgmii2_tx_pwrup_c), .tx_serdes_rst_c(sgmii2_tx_serdes_rst_c), - .txi_clk(sgmii2_txi_clk)); + .txi_clk(sgmii2_txi_clk),.tx_full_clk()); sgmii3 sgmii3_inst (.rx_cv_err({sgmii3_rx_cv_err}), .rx_disp_err({sgmii3_rx_disp_err}), .rx_k({sgmii3_rx_k}), .rxdata({sgmii3_rxdata}), .sci_addr({sgmii2_sci_addr}), .sci_rddata({i_sgmii3_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}), @@ -314,7 +314,7 @@ module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata, .serdes_pdb(sgmii2_serdes_pdb), .serdes_rst_dual_c(sgmii3_serdes_rst_dual_c), .signal_detect_c(sgmii3_signal_detect_c), .tx_pclk(sgmii3_tx_pclk), .tx_pcs_rst_c(sgmii3_tx_pcs_rst_c), .tx_pwrup_c(sgmii3_tx_pwrup_c), - .tx_serdes_rst_c(sgmii3_tx_serdes_rst_c), .txi_clk(sgmii3_txi_clk)); + .tx_serdes_rst_c(sgmii3_tx_serdes_rst_c), .txi_clk(sgmii3_txi_clk),.tx_full_clk()); endmodule diff --git a/clarity/pcs/pcs_tmpl.v b/clarity/pcs/pcs_tmpl.v index b181d80..2250f1a 100644 --- a/clarity/pcs/pcs_tmpl.v +++ b/clarity/pcs/pcs_tmpl.v @@ -1,15 +1,27 @@ //Verilog instantiation template -pcs _inst (.sgmii1_rx_cv_err(), .sgmii1_rx_disp_err(), .sgmii1_rx_k(), - .sgmii1_rxdata(), .sgmii1_tx_disp_correct(), .sgmii1_tx_k(), .sgmii1_txdata(), - .sgmii1_xmit(), .sgmii1_ctc_del_s(), .sgmii1_ctc_ins_s(), .sgmii1_ctc_orun_s(), - .sgmii1_ctc_urun_s(), .sgmii1_hdinn(), .sgmii1_hdinp(), .sgmii1_hdoutn(), - .sgmii1_hdoutp(), .sgmii1_lsm_status_s(), .sgmii1_rst_dual_c(), .sgmii1_rx_cdr_lol_s(), - .sgmii1_rx_los_low_s(), .sgmii1_rx_pcs_rst_c(), .sgmii1_rx_pwrup_c(), - .sgmii1_rx_serdes_rst_c(), .sgmii1_sci_en(), .sgmii1_sci_sel(), .sgmii1_serdes_pdb(), - .sgmii1_serdes_rst_dual_c(), .sgmii1_signal_detect_c(), .sgmii1_tx_pclk(), - .sgmii1_tx_pcs_rst_c(), .sgmii1_tx_pwrup_c(), .sgmii1_tx_serdes_rst_c(), - .sgmii1_txi_clk(), .sgmii2_rx_cv_err(), .sgmii2_rx_disp_err(), .sgmii2_rx_k(), +pcs _inst (.refclk0_refclkn(), .refclk0_refclkp(), .sgmii1_rx_cv_err(), + .sgmii1_rx_disp_err(), .sgmii1_rx_k(), .sgmii1_rxdata(), .sgmii1_tx_disp_correct(), + .sgmii1_tx_k(), .sgmii1_txdata(), .sgmii1_xmit(), .sgmii1_ctc_del_s(), + .sgmii1_ctc_ins_s(), .sgmii1_ctc_orun_s(), .sgmii1_ctc_urun_s(), .sgmii1_hdinn(), + .sgmii1_hdinp(), .sgmii1_hdoutn(), .sgmii1_hdoutp(), .sgmii1_lsm_status_s(), + .sgmii1_rst_dual_c(), .sgmii1_rx_cdr_lol_s(), .sgmii1_rx_los_low_s(), + .sgmii1_rx_pcs_rst_c(), .sgmii1_rx_pwrup_c(), .sgmii1_rx_serdes_rst_c(), + .sgmii1_sci_en(), .sgmii1_sci_sel(), .sgmii1_serdes_pdb(), .sgmii1_serdes_rst_dual_c(), + .sgmii1_signal_detect_c(), .sgmii1_tx_pclk(), .sgmii1_tx_pcs_rst_c(), + .sgmii1_tx_pwrup_c(), .sgmii1_tx_serdes_rst_c(), .sgmii1_txi_clk(), + .sgmii0_rx_cv_err(), .sgmii0_rx_disp_err(), .sgmii0_rx_k(), .sgmii0_rxdata(), + .sgmii0_sci_addr(), .sgmii0_sci_wrdata(), .sgmii0_tx_disp_correct(), + .sgmii0_tx_k(), .sgmii0_txdata(), .sgmii0_xmit(), .sgmii0_ctc_del_s(), + .sgmii0_ctc_ins_s(), .sgmii0_ctc_orun_s(), .sgmii0_ctc_urun_s(), .sgmii0_cyawstn(), + .sgmii0_hdinn(), .sgmii0_hdinp(), .sgmii0_hdoutn(), .sgmii0_hdoutp(), + .sgmii0_lsm_status_s(), .sgmii0_pll_lol(), .sgmii0_rst_dual_c(), .sgmii0_rx_cdr_lol_s(), + .sgmii0_rx_los_low_s(), .sgmii0_rx_pcs_rst_c(), .sgmii0_rx_pwrup_c(), + .sgmii0_rx_serdes_rst_c(), .sgmii0_sci_en(), .sgmii0_sci_en_dual(), + .sgmii0_sci_rd(), .sgmii0_sci_sel(), .sgmii0_sci_sel_dual(), .sgmii0_sci_wrn(), + .sgmii0_serdes_rst_dual_c(), .sgmii0_signal_detect_c(), .sgmii0_tx_pclk(), + .sgmii0_tx_pcs_rst_c(), .sgmii0_tx_pwrup_c(), .sgmii0_tx_serdes_rst_c(), + .sgmii0_txi_clk(), .sgmii2_rx_cv_err(), .sgmii2_rx_disp_err(), .sgmii2_rx_k(), .sgmii2_rxdata(), .sgmii2_tx_disp_correct(), .sgmii2_tx_k(), .sgmii2_txdata(), .sgmii2_xmit(), .sgmii2_ctc_del_s(), .sgmii2_ctc_ins_s(), .sgmii2_ctc_orun_s(), .sgmii2_ctc_urun_s(), .sgmii2_hdinn(), .sgmii2_hdinp(), .sgmii2_hdoutn(), @@ -29,16 +41,4 @@ pcs _inst (.sgmii1_rx_cv_err(), .sgmii1_rx_disp_err(), .sgmii1_rx_k(), .sgmii3_rx_pwrup_c(), .sgmii3_rx_serdes_rst_c(), .sgmii3_rxrefclk(), .sgmii3_sci_en(), .sgmii3_sci_sel(), .sgmii3_serdes_rst_dual_c(), .sgmii3_signal_detect_c(), .sgmii3_tx_pclk(), .sgmii3_tx_pcs_rst_c(), - .sgmii3_tx_pwrup_c(), .sgmii3_tx_serdes_rst_c(), .sgmii3_txi_clk(), - .refclk0_refclkn(), .refclk0_refclkp(), .sgmii0_rx_cv_err(), .sgmii0_rx_disp_err(), - .sgmii0_rx_k(), .sgmii0_rxdata(), .sgmii0_sci_addr(), .sgmii0_sci_wrdata(), - .sgmii0_tx_disp_correct(), .sgmii0_tx_k(), .sgmii0_txdata(), .sgmii0_xmit(), - .sgmii0_ctc_del_s(), .sgmii0_ctc_ins_s(), .sgmii0_ctc_orun_s(), .sgmii0_ctc_urun_s(), - .sgmii0_cyawstn(), .sgmii0_hdinn(), .sgmii0_hdinp(), .sgmii0_hdoutn(), - .sgmii0_hdoutp(), .sgmii0_lsm_status_s(), .sgmii0_pll_lol(), .sgmii0_rst_dual_c(), - .sgmii0_rx_cdr_lol_s(), .sgmii0_rx_los_low_s(), .sgmii0_rx_pcs_rst_c(), - .sgmii0_rx_pwrup_c(), .sgmii0_rx_serdes_rst_c(), .sgmii0_sci_en(), - .sgmii0_sci_en_dual(), .sgmii0_sci_rd(), .sgmii0_sci_sel(), .sgmii0_sci_sel_dual(), - .sgmii0_sci_wrn(), .sgmii0_serdes_rst_dual_c(), .sgmii0_signal_detect_c(), - .sgmii0_tx_pclk(), .sgmii0_tx_pcs_rst_c(), .sgmii0_tx_pwrup_c(), .sgmii0_tx_serdes_rst_c(), - .sgmii0_txi_clk());
\ No newline at end of file + .sgmii3_tx_pwrup_c(), .sgmii3_tx_serdes_rst_c(), .sgmii3_txi_clk());
\ No newline at end of file diff --git a/clarity/pcs/refclk0/refclk0.lpc b/clarity/pcs/refclk0/refclk0.lpc index 4e2184e..1894b2d 100644 --- a/clarity/pcs/refclk0/refclk0.lpc +++ b/clarity/pcs/refclk0/refclk0.lpc @@ -11,11 +11,11 @@ CoreName=EXTREF CoreRevision=1.1 CoreStatus=Demo CoreType=LPM -Date=10/17/2017 +Date=03/06/2020 ModuleName=refclk0 ParameterFileVersion=1.0 SourceFormat=verilog -Time=18:21:09 +Time=20:20:44 VendorName=Lattice Semiconductor Corporation [Parameters] Destination=Synplicity diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v index 7fe46e2..edeb81f 100644 --- a/clarity/pcs/refclk0/refclk0.v +++ b/clarity/pcs/refclk0/refclk0.v @@ -1,5 +1,5 @@ // Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65 -// Netlist written on Tue Oct 17 18:22:54 2017 +// Netlist written on Fri Mar 06 20:20:57 2020 // // Verilog Description of module refclk0 // diff --git a/clarity/pcs/sgmii0/sgmii0.fdc b/clarity/pcs/sgmii0/sgmii0.fdc index 292bc0f..6fbcac9 100644 --- a/clarity/pcs/sgmii0/sgmii0.fdc +++ b/clarity/pcs/sgmii0/sgmii0.fdc @@ -1,3 +1,2 @@ -###==== Start Generation +###==== Start Configuration -define_attribute {i:Lane0} {loc} {DCU0_CH0} diff --git a/clarity/pcs/sgmii0/sgmii0.lpc b/clarity/pcs/sgmii0/sgmii0.lpc index 0aea3d2..5c06b05 100644 --- a/clarity/pcs/sgmii0/sgmii0.lpc +++ b/clarity/pcs/sgmii0/sgmii0.lpc @@ -11,11 +11,11 @@ CoreName=PCS CoreRevision=8.2 CoreStatus=Demo CoreType=LPM -Date=02/08/2019 +Date=03/21/2020 ModuleName=sgmii0 ParameterFileVersion=1.0 SourceFormat=verilog -Time=18:42:05 +Time=21:48:39 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -25,8 +25,8 @@ VendorName=Lattice Semiconductor Corporation CDRLOLACTION=Full Recalibration CDRLOLRANGE=0 CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 +CDR_MULT=10X +CDR_REF_RATE=125.0000 CH_MODE=Rx and Tx Destination=Synplicity EDIF=1 @@ -44,7 +44,7 @@ PROTOCOL=GbE PWAIT_RX_RDY=3000 PWAIT_TX_RDY=3000 RCSRC=Disabled -REFCLK_RATE=50.0000 +REFCLK_RATE=125.0000 RSTSEQSEL=Disabled RX8B10B=Enabled RXCOMMAA=1010000011 @@ -80,7 +80,7 @@ TXFIFO_ENABLE=Enabled TXINVPOL=Invert TXLDR=Off TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X +TXPLLMULT=10X TX_DATA_WIDTH=8/10-Bit TX_FICLK_RATE=125.0000 TX_LINE_RATE=1.2500 diff --git a/clarity/pcs/sgmii0/sgmii0.v b/clarity/pcs/sgmii0/sgmii0.v index e2b5903..8cbf73e 100644 --- a/clarity/pcs/sgmii0/sgmii0.v +++ b/clarity/pcs/sgmii0/sgmii0.v @@ -1,12 +1,12 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 -// Netlist written on Sun Nov 18 17:44:07 2018 +// Verilog netlist produced by program ASBGen: Ports rev. 2.32, Attr. rev. 2.70 +// Netlist written on Sat Mar 21 21:49:34 2020 // // Verilog Description of module sgmii0 // `timescale 1ns/1ps module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, - tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + tx_pclk, txi_clk, tx_full_clk, txdata, tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, @@ -21,6 +21,7 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, input rxrefclk; output tx_pclk; input txi_clk; + output tx_full_clk; input [7:0]txdata; input [0:0]tx_k; input [0:0]xmit; @@ -66,18 +67,18 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, - n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n42, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, - n94, n95, n96, n97, n98, n99, n100, n101, _Z; + n94, n95, n96, n97, n98, n99, n100, _Z; DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(tx_pclk), .CH1_FF_RXI_CLK(1'b1), - .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_pclk), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_full_clk), .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), @@ -125,48 +126,48 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), - .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n47), .CH0_HDOUTN(hdoutn), - .CH1_HDOUTN(n48), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), + .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n46), .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n47), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n5), - .CH1_FF_RX_F_CLK(n49), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n50), - .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n51), .CH0_FF_TX_H_CLK(n8), - .CH1_FF_TX_H_CLK(n52), .CH0_FF_RX_PCLK(n9), .CH1_FF_RX_PCLK(n53), - .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n54), .CH0_FF_RX_D_0(rxdata[0]), - .CH1_FF_RX_D_0(n55), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n56), - .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n57), .CH0_FF_RX_D_3(rxdata[3]), - .CH1_FF_RX_D_3(n58), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n59), - .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n60), .CH0_FF_RX_D_6(rxdata[6]), - .CH1_FF_RX_D_6(n61), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n62), - .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n63), .CH0_FF_RX_D_9(rx_disp_err[0]), - .CH1_FF_RX_D_9(n64), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n65), - .CH0_FF_RX_D_11(n10), .CH1_FF_RX_D_11(n66), .CH0_FF_RX_D_12(n67), - .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), - .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), - .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), - .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), - .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), - .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), - .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), - .CH0_FF_RX_D_23(n11), .CH1_FF_RX_D_23(n89), .CH0_FFS_PCIE_DONE(n12), - .CH1_FFS_PCIE_DONE(n90), .CH0_FFS_PCIE_CON(n13), .CH1_FFS_PCIE_CON(n91), - .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n92), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), - .CH1_FFS_LS_SYNC_STATUS(n93), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), - .CH1_FFS_CC_UNDERRUN(n94), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n95), - .CH0_FFS_RXFBFIFO_ERROR(n14), .CH1_FFS_RXFBFIFO_ERROR(n96), .CH0_FFS_TXFBFIFO_ERROR(n15), - .CH1_FFS_TXFBFIFO_ERROR(n97), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n98), - .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n99), .CH0_FFS_SKP_DELETED(ctc_del_s), - .CH1_FFS_SKP_DELETED(n100), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .CH1_FF_RX_F_CLK(n48), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n49), + .CH0_FF_TX_F_CLK(tx_full_clk), .CH1_FF_TX_F_CLK(n50), .CH0_FF_TX_H_CLK(n7), + .CH1_FF_TX_H_CLK(n51), .CH0_FF_RX_PCLK(n8), .CH1_FF_RX_PCLK(n52), + .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n53), .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n54), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n55), + .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n56), .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n57), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n58), + .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n59), .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n60), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n61), + .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n62), .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n63), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n64), + .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n65), .CH0_FF_RX_D_12(n66), + .CH1_FF_RX_D_12(n67), .CH0_FF_RX_D_13(n68), .CH1_FF_RX_D_13(n69), + .CH0_FF_RX_D_14(n70), .CH1_FF_RX_D_14(n71), .CH0_FF_RX_D_15(n72), + .CH1_FF_RX_D_15(n73), .CH0_FF_RX_D_16(n74), .CH1_FF_RX_D_16(n75), + .CH0_FF_RX_D_17(n76), .CH1_FF_RX_D_17(n77), .CH0_FF_RX_D_18(n78), + .CH1_FF_RX_D_18(n79), .CH0_FF_RX_D_19(n80), .CH1_FF_RX_D_19(n81), + .CH0_FF_RX_D_20(n82), .CH1_FF_RX_D_20(n83), .CH0_FF_RX_D_21(n84), + .CH1_FF_RX_D_21(n85), .CH0_FF_RX_D_22(n86), .CH1_FF_RX_D_22(n87), + .CH0_FF_RX_D_23(n10), .CH1_FF_RX_D_23(n88), .CH0_FFS_PCIE_DONE(n11), + .CH1_FFS_PCIE_DONE(n89), .CH0_FFS_PCIE_CON(n12), .CH1_FFS_PCIE_CON(n90), + .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n91), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n92), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n93), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n94), + .CH0_FFS_RXFBFIFO_ERROR(n13), .CH1_FFS_RXFBFIFO_ERROR(n95), .CH0_FFS_TXFBFIFO_ERROR(n14), + .CH1_FFS_TXFBFIFO_ERROR(n96), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n97), + .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n98), .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n99), .CH0_LDR_RX2CORE(n100), .CH1_LDR_RX2CORE(_Z), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), - .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), - .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), - .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), - .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), - .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), - .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), - .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), - .D_REFCLKI(pll_refclki), .D_FFS_PLOL(pll_lol)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; + .D_SCAN_OUT_0(n15), .D_SCAN_OUT_1(n16), .D_SCAN_OUT_2(n17), .D_SCAN_OUT_3(n18), + .D_SCAN_OUT_4(n19), .D_SCAN_OUT_5(n20), .D_SCAN_OUT_6(n21), .D_SCAN_OUT_7(n22), + .D_COUT0(n23), .D_COUT1(n24), .D_COUT2(n25), .D_COUT3(n26), + .D_COUT4(n27), .D_COUT5(n28), .D_COUT6(n29), .D_COUT7(n30), + .D_COUT8(n31), .D_COUT9(n32), .D_COUT10(n33), .D_COUT11(n34), + .D_COUT12(n35), .D_COUT13(n36), .D_COUT14(n37), .D_COUT15(n38), + .D_COUT16(n39), .D_COUT17(n40), .D_COUT18(n41), .D_COUT19(n42), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n45)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; defparam DCU0_inst.D_MACROPDB = "0b1"; defparam DCU0_inst.D_IB_PWDNB = "0b1"; defparam DCU0_inst.D_XGE_MODE = "0b0"; @@ -314,7 +315,7 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, defparam DCU0_inst.D_CMUSETBIASI = "0b00"; defparam DCU0_inst.D_SETPLLRC = "0d1"; defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; - defparam DCU0_inst.D_REFCK_MODE = "0b100"; + defparam DCU0_inst.D_REFCK_MODE = "0b001"; defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; defparam DCU0_inst.D_RG_EN = "0b0"; @@ -361,7 +362,7 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n40 = 1'bz; assign n41 = 1'bz; assign n42 = 1'bz; - assign n43 = 1'bz; + assign n45 = 1'bz; assign n46 = 1'bz; assign n47 = 1'bz; assign n48 = 1'bz; @@ -417,19 +418,18 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n98 = 1'bz; assign n99 = 1'bz; assign n100 = 1'bz; - assign n101 = 1'bz; assign _Z = 1'bz; sgmii0sll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), - .slo_plol()); + .slo_plol(pll_lol)); defparam sll_inst.PPROTOCOL = "GBE"; defparam sll_inst.PLOL_SETTING = 0; defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; defparam sll_inst.PPCIE_MAX_RATE = "2.5"; - defparam sll_inst.PDIFF_VAL_LOCK = 98; - defparam sll_inst.PDIFF_VAL_UNLOCK = 196; - defparam sll_inst.PPCLK_TC = 327680; + defparam sll_inst.PDIFF_VAL_LOCK = 20; + defparam sll_inst.PDIFF_VAL_UNLOCK = 40; + defparam sll_inst.PPCLK_TC = 65536; defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; defparam sll_inst.PPCLK_DIV11_TC = 0; diff --git a/clarity/pcs/sgmii1/sgmii1.fdc b/clarity/pcs/sgmii1/sgmii1.fdc index c667056..6fbcac9 100644 --- a/clarity/pcs/sgmii1/sgmii1.fdc +++ b/clarity/pcs/sgmii1/sgmii1.fdc @@ -1,3 +1,2 @@ -###==== Start Generation +###==== Start Configuration -define_attribute {i:Lane0} {loc} {DCU0_CH1} diff --git a/clarity/pcs/sgmii1/sgmii1.lpc b/clarity/pcs/sgmii1/sgmii1.lpc index ac31555..007e691 100644 --- a/clarity/pcs/sgmii1/sgmii1.lpc +++ b/clarity/pcs/sgmii1/sgmii1.lpc @@ -11,11 +11,11 @@ CoreName=PCS CoreRevision=8.2 CoreStatus=Demo CoreType=LPM -Date=11/18/2018 +Date=03/21/2020 ModuleName=sgmii1 ParameterFileVersion=1.0 SourceFormat=verilog -Time=17:42:50 +Time=21:47:13 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -25,8 +25,8 @@ VendorName=Lattice Semiconductor Corporation CDRLOLACTION=Full Recalibration CDRLOLRANGE=0 CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 +CDR_MULT=10X +CDR_REF_RATE=125.0000 CH_MODE=Rx and Tx Destination=Synplicity EDIF=1 @@ -44,7 +44,7 @@ PROTOCOL=GbE PWAIT_RX_RDY=3000 PWAIT_TX_RDY=3000 RCSRC=Disabled -REFCLK_RATE=50.0000 +REFCLK_RATE=125.0000 RSTSEQSEL=Disabled RX8B10B=Enabled RXCOMMAA=1010000011 @@ -80,7 +80,7 @@ TXFIFO_ENABLE=Enabled TXINVPOL=Invert TXLDR=Off TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X +TXPLLMULT=10X TX_DATA_WIDTH=8/10-Bit TX_FICLK_RATE=125.0000 TX_LINE_RATE=1.2500 diff --git a/clarity/pcs/sgmii1/sgmii1.v b/clarity/pcs/sgmii1/sgmii1.v index 648808a..dbb36df 100644 --- a/clarity/pcs/sgmii1/sgmii1.v +++ b/clarity/pcs/sgmii1/sgmii1.v @@ -1,12 +1,12 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 -// Netlist written on Sun Nov 18 17:44:07 2018 +// Verilog netlist produced by program ASBGen: Ports rev. 2.32, Attr. rev. 2.70 +// Netlist written on Sat Mar 21 21:49:34 2020 // // Verilog Description of module sgmii1 // `timescale 1ns/1ps module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, - tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + tx_pclk, txi_clk, tx_full_clk, txdata, tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, @@ -21,6 +21,7 @@ module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, input rxrefclk; output tx_pclk; input txi_clk; + output tx_full_clk; input [7:0]txdata; input [0:0]tx_k; input [0:0]xmit; @@ -64,19 +65,19 @@ module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, - n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n42, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, - n94, n95, n96, n97, n98, n99, n100, n101, _Z; + n94, n95, n96, n97, n98, n99, n100, _Z; DCUA DCU0_inst (.CH0_HDINP(1'b0), .CH1_HDINP(hdinp), .CH0_HDINN(1'b0), .CH1_HDINN(hdinn), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(1'b0), .CH1_RX_REFCLK(rxrefclk), .CH0_FF_RXI_CLK(1'b1), .CH1_FF_RXI_CLK(tx_pclk), .CH0_FF_TXI_CLK(1'b1), .CH1_FF_TXI_CLK(txi_clk), .CH0_FF_EBRD_CLK(1'b1), - .CH1_FF_EBRD_CLK(tx_pclk), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), + .CH1_FF_EBRD_CLK(tx_full_clk), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), .CH0_FF_TX_D_1(1'b0), .CH1_FF_TX_D_1(txdata[1]), .CH0_FF_TX_D_2(1'b0), .CH1_FF_TX_D_2(txdata[2]), .CH0_FF_TX_D_3(1'b0), .CH1_FF_TX_D_3(txdata[3]), .CH0_FF_TX_D_4(1'b0), .CH1_FF_TX_D_4(txdata[4]), .CH0_FF_TX_D_5(1'b0), @@ -123,48 +124,48 @@ module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), - .D_CIN11(1'b0), .CH0_HDOUTP(n47), .CH1_HDOUTP(hdoutp), .CH0_HDOUTN(n48), + .D_CIN11(1'b0), .CH0_HDOUTP(n46), .CH1_HDOUTP(hdoutp), .CH0_HDOUTN(n47), .CH1_HDOUTN(hdoutn), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), - .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n49), - .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n50), .CH1_FF_RX_H_CLK(n6), - .CH0_FF_TX_F_CLK(n51), .CH1_FF_TX_F_CLK(n7), .CH0_FF_TX_H_CLK(n52), - .CH1_FF_TX_H_CLK(n8), .CH0_FF_RX_PCLK(n53), .CH1_FF_RX_PCLK(n9), - .CH0_FF_TX_PCLK(n54), .CH1_FF_TX_PCLK(tx_pclk), .CH0_FF_RX_D_0(n55), - .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n56), .CH1_FF_RX_D_1(rxdata[1]), - .CH0_FF_RX_D_2(n57), .CH1_FF_RX_D_2(rxdata[2]), .CH0_FF_RX_D_3(n58), - .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n59), .CH1_FF_RX_D_4(rxdata[4]), - .CH0_FF_RX_D_5(n60), .CH1_FF_RX_D_5(rxdata[5]), .CH0_FF_RX_D_6(n61), - .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n62), .CH1_FF_RX_D_7(rxdata[7]), - .CH0_FF_RX_D_8(n63), .CH1_FF_RX_D_8(rx_k[0]), .CH0_FF_RX_D_9(n64), - .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n65), .CH1_FF_RX_D_10(rx_cv_err[0]), - .CH0_FF_RX_D_11(n66), .CH1_FF_RX_D_11(n10), .CH0_FF_RX_D_12(n67), - .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), - .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), - .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), - .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), - .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), - .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), - .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), - .CH0_FF_RX_D_23(n89), .CH1_FF_RX_D_23(n11), .CH0_FFS_PCIE_DONE(n90), - .CH1_FFS_PCIE_DONE(n12), .CH0_FFS_PCIE_CON(n91), .CH1_FFS_PCIE_CON(n13), - .CH0_FFS_RLOS(n92), .CH1_FFS_RLOS(rx_los_low_s), .CH0_FFS_LS_SYNC_STATUS(n93), - .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), .CH0_FFS_CC_UNDERRUN(n94), - .CH1_FFS_CC_UNDERRUN(ctc_urun_s), .CH0_FFS_CC_OVERRUN(n95), .CH1_FFS_CC_OVERRUN(ctc_orun_s), - .CH0_FFS_RXFBFIFO_ERROR(n96), .CH1_FFS_RXFBFIFO_ERROR(n14), .CH0_FFS_TXFBFIFO_ERROR(n97), - .CH1_FFS_TXFBFIFO_ERROR(n15), .CH0_FFS_RLOL(n98), .CH1_FFS_RLOL(rx_cdr_lol_s), - .CH0_FFS_SKP_ADDED(n99), .CH1_FFS_SKP_ADDED(ctc_ins_s), .CH0_FFS_SKP_DELETED(n100), - .CH1_FFS_SKP_DELETED(ctc_del_s), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n48), + .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n49), .CH1_FF_RX_H_CLK(n6), + .CH0_FF_TX_F_CLK(n50), .CH1_FF_TX_F_CLK(tx_full_clk), .CH0_FF_TX_H_CLK(n51), + .CH1_FF_TX_H_CLK(n7), .CH0_FF_RX_PCLK(n52), .CH1_FF_RX_PCLK(n8), + .CH0_FF_TX_PCLK(n53), .CH1_FF_TX_PCLK(tx_pclk), .CH0_FF_RX_D_0(n54), + .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n55), .CH1_FF_RX_D_1(rxdata[1]), + .CH0_FF_RX_D_2(n56), .CH1_FF_RX_D_2(rxdata[2]), .CH0_FF_RX_D_3(n57), + .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n58), .CH1_FF_RX_D_4(rxdata[4]), + .CH0_FF_RX_D_5(n59), .CH1_FF_RX_D_5(rxdata[5]), .CH0_FF_RX_D_6(n60), + .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n61), .CH1_FF_RX_D_7(rxdata[7]), + .CH0_FF_RX_D_8(n62), .CH1_FF_RX_D_8(rx_k[0]), .CH0_FF_RX_D_9(n63), + .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n64), .CH1_FF_RX_D_10(rx_cv_err[0]), + .CH0_FF_RX_D_11(n65), .CH1_FF_RX_D_11(n9), .CH0_FF_RX_D_12(n66), + .CH1_FF_RX_D_12(n67), .CH0_FF_RX_D_13(n68), .CH1_FF_RX_D_13(n69), + .CH0_FF_RX_D_14(n70), .CH1_FF_RX_D_14(n71), .CH0_FF_RX_D_15(n72), + .CH1_FF_RX_D_15(n73), .CH0_FF_RX_D_16(n74), .CH1_FF_RX_D_16(n75), + .CH0_FF_RX_D_17(n76), .CH1_FF_RX_D_17(n77), .CH0_FF_RX_D_18(n78), + .CH1_FF_RX_D_18(n79), .CH0_FF_RX_D_19(n80), .CH1_FF_RX_D_19(n81), + .CH0_FF_RX_D_20(n82), .CH1_FF_RX_D_20(n83), .CH0_FF_RX_D_21(n84), + .CH1_FF_RX_D_21(n85), .CH0_FF_RX_D_22(n86), .CH1_FF_RX_D_22(n87), + .CH0_FF_RX_D_23(n88), .CH1_FF_RX_D_23(n10), .CH0_FFS_PCIE_DONE(n89), + .CH1_FFS_PCIE_DONE(n11), .CH0_FFS_PCIE_CON(n90), .CH1_FFS_PCIE_CON(n12), + .CH0_FFS_RLOS(n91), .CH1_FFS_RLOS(rx_los_low_s), .CH0_FFS_LS_SYNC_STATUS(n92), + .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), .CH0_FFS_CC_UNDERRUN(n93), + .CH1_FFS_CC_UNDERRUN(ctc_urun_s), .CH0_FFS_CC_OVERRUN(n94), .CH1_FFS_CC_OVERRUN(ctc_orun_s), + .CH0_FFS_RXFBFIFO_ERROR(n95), .CH1_FFS_RXFBFIFO_ERROR(n13), .CH0_FFS_TXFBFIFO_ERROR(n96), + .CH1_FFS_TXFBFIFO_ERROR(n14), .CH0_FFS_RLOL(n97), .CH1_FFS_RLOL(rx_cdr_lol_s), + .CH0_FFS_SKP_ADDED(n98), .CH1_FFS_SKP_ADDED(ctc_ins_s), .CH0_FFS_SKP_DELETED(n99), + .CH1_FFS_SKP_DELETED(ctc_del_s), .CH0_LDR_RX2CORE(n100), .CH1_LDR_RX2CORE(_Z), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), - .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), - .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), - .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), - .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), - .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), - .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), - .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), - .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n46)) /* synthesis LOC=DCU0 CHAN=CH1 */ ; + .D_SCAN_OUT_0(n15), .D_SCAN_OUT_1(n16), .D_SCAN_OUT_2(n17), .D_SCAN_OUT_3(n18), + .D_SCAN_OUT_4(n19), .D_SCAN_OUT_5(n20), .D_SCAN_OUT_6(n21), .D_SCAN_OUT_7(n22), + .D_COUT0(n23), .D_COUT1(n24), .D_COUT2(n25), .D_COUT3(n26), + .D_COUT4(n27), .D_COUT5(n28), .D_COUT6(n29), .D_COUT7(n30), + .D_COUT8(n31), .D_COUT9(n32), .D_COUT10(n33), .D_COUT11(n34), + .D_COUT12(n35), .D_COUT13(n36), .D_COUT14(n37), .D_COUT15(n38), + .D_COUT16(n39), .D_COUT17(n40), .D_COUT18(n41), .D_COUT19(n42), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n45)) /* synthesis LOC=DCU0 CHAN=CH1 */ ; defparam DCU0_inst.D_MACROPDB = "0b1"; defparam DCU0_inst.D_IB_PWDNB = "0b1"; defparam DCU0_inst.D_XGE_MODE = "0b0"; @@ -312,7 +313,7 @@ module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, defparam DCU0_inst.D_CMUSETBIASI = "0b00"; defparam DCU0_inst.D_SETPLLRC = "0d1"; defparam DCU0_inst.CH1_RX_RATE_SEL = "0d8"; - defparam DCU0_inst.D_REFCK_MODE = "0b100"; + defparam DCU0_inst.D_REFCK_MODE = "0b001"; defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; defparam DCU0_inst.D_RG_EN = "0b0"; @@ -359,7 +360,7 @@ module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n40 = 1'bz; assign n41 = 1'bz; assign n42 = 1'bz; - assign n43 = 1'bz; + assign n45 = 1'bz; assign n46 = 1'bz; assign n47 = 1'bz; assign n48 = 1'bz; @@ -415,7 +416,6 @@ module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n98 = 1'bz; assign n99 = 1'bz; assign n100 = 1'bz; - assign n101 = 1'bz; assign _Z = 1'bz; endmodule diff --git a/clarity/pcs/sgmii2/sgmii2.fdc b/clarity/pcs/sgmii2/sgmii2.fdc index 29b09af..6fbcac9 100644 --- a/clarity/pcs/sgmii2/sgmii2.fdc +++ b/clarity/pcs/sgmii2/sgmii2.fdc @@ -1,3 +1,2 @@ -###==== Start Generation +###==== Start Configuration -define_attribute {i:Lane0} {loc} {DCU1_CH0} diff --git a/clarity/pcs/sgmii2/sgmii2.lpc b/clarity/pcs/sgmii2/sgmii2.lpc index 5e8a34b..291651a 100644 --- a/clarity/pcs/sgmii2/sgmii2.lpc +++ b/clarity/pcs/sgmii2/sgmii2.lpc @@ -11,11 +11,11 @@ CoreName=PCS CoreRevision=8.2 CoreStatus=Demo CoreType=LPM -Date=03/15/2019 +Date=03/21/2020 ModuleName=sgmii2 ParameterFileVersion=1.0 SourceFormat=verilog -Time=18:46:19 +Time=21:49:06 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -25,8 +25,8 @@ VendorName=Lattice Semiconductor Corporation CDRLOLACTION=Full Recalibration CDRLOLRANGE=0 CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 +CDR_MULT=10X +CDR_REF_RATE=125.0000 CH_MODE=Rx and Tx Destination=Synplicity EDIF=1 @@ -44,7 +44,7 @@ PROTOCOL=GbE PWAIT_RX_RDY=3000 PWAIT_TX_RDY=3000 RCSRC=Disabled -REFCLK_RATE=50.0000 +REFCLK_RATE=125.0000 RSTSEQSEL=Disabled RX8B10B=Enabled RXCOMMAA=1010000011 @@ -80,7 +80,7 @@ TXFIFO_ENABLE=Enabled TXINVPOL=Non-invert TXLDR=Off TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X +TXPLLMULT=10X TX_DATA_WIDTH=8/10-Bit TX_FICLK_RATE=125.0000 TX_LINE_RATE=1.2500 diff --git a/clarity/pcs/sgmii2/sgmii2.v b/clarity/pcs/sgmii2/sgmii2.v index 77abaf2..acc9184 100644 --- a/clarity/pcs/sgmii2/sgmii2.v +++ b/clarity/pcs/sgmii2/sgmii2.v @@ -1,12 +1,12 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 -// Netlist written on Fri Mar 15 18:48:22 2019 +// Verilog netlist produced by program ASBGen: Ports rev. 2.32, Attr. rev. 2.70 +// Netlist written on Sat Mar 21 21:49:34 2020 // // Verilog Description of module sgmii2 // `timescale 1ns/1ps module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, - tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + tx_pclk, txi_clk, tx_full_clk, txdata, tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, @@ -21,6 +21,7 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, input rxrefclk; output tx_pclk; input txi_clk; + output tx_full_clk; input [7:0]txdata; input [0:0]tx_k; input [0:0]xmit; @@ -66,18 +67,18 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, - n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n42, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, - n94, n95, n96, n97, n98, n99, n100, n101, _Z; + n94, n95, n96, n97, n98, n99, n100, _Z; DCUA DCU1_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(tx_pclk), .CH1_FF_RXI_CLK(1'b1), - .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_pclk), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_full_clk), .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), @@ -125,48 +126,48 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), - .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n47), .CH0_HDOUTN(hdoutn), - .CH1_HDOUTN(n48), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), + .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n46), .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n47), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n5), - .CH1_FF_RX_F_CLK(n49), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n50), - .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n51), .CH0_FF_TX_H_CLK(n8), - .CH1_FF_TX_H_CLK(n52), .CH0_FF_RX_PCLK(n9), .CH1_FF_RX_PCLK(n53), - .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n54), .CH0_FF_RX_D_0(rxdata[0]), - .CH1_FF_RX_D_0(n55), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n56), - .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n57), .CH0_FF_RX_D_3(rxdata[3]), - .CH1_FF_RX_D_3(n58), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n59), - .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n60), .CH0_FF_RX_D_6(rxdata[6]), - .CH1_FF_RX_D_6(n61), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n62), - .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n63), .CH0_FF_RX_D_9(rx_disp_err[0]), - .CH1_FF_RX_D_9(n64), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n65), - .CH0_FF_RX_D_11(n10), .CH1_FF_RX_D_11(n66), .CH0_FF_RX_D_12(n67), - .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), - .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), - .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), - .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), - .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), - .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), - .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), - .CH0_FF_RX_D_23(n11), .CH1_FF_RX_D_23(n89), .CH0_FFS_PCIE_DONE(n12), - .CH1_FFS_PCIE_DONE(n90), .CH0_FFS_PCIE_CON(n13), .CH1_FFS_PCIE_CON(n91), - .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n92), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), - .CH1_FFS_LS_SYNC_STATUS(n93), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), - .CH1_FFS_CC_UNDERRUN(n94), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n95), - .CH0_FFS_RXFBFIFO_ERROR(n14), .CH1_FFS_RXFBFIFO_ERROR(n96), .CH0_FFS_TXFBFIFO_ERROR(n15), - .CH1_FFS_TXFBFIFO_ERROR(n97), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n98), - .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n99), .CH0_FFS_SKP_DELETED(ctc_del_s), - .CH1_FFS_SKP_DELETED(n100), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .CH1_FF_RX_F_CLK(n48), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n49), + .CH0_FF_TX_F_CLK(tx_full_clk), .CH1_FF_TX_F_CLK(n50), .CH0_FF_TX_H_CLK(n7), + .CH1_FF_TX_H_CLK(n51), .CH0_FF_RX_PCLK(n8), .CH1_FF_RX_PCLK(n52), + .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n53), .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n54), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n55), + .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n56), .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n57), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n58), + .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n59), .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n60), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n61), + .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n62), .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n63), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n64), + .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n65), .CH0_FF_RX_D_12(n66), + .CH1_FF_RX_D_12(n67), .CH0_FF_RX_D_13(n68), .CH1_FF_RX_D_13(n69), + .CH0_FF_RX_D_14(n70), .CH1_FF_RX_D_14(n71), .CH0_FF_RX_D_15(n72), + .CH1_FF_RX_D_15(n73), .CH0_FF_RX_D_16(n74), .CH1_FF_RX_D_16(n75), + .CH0_FF_RX_D_17(n76), .CH1_FF_RX_D_17(n77), .CH0_FF_RX_D_18(n78), + .CH1_FF_RX_D_18(n79), .CH0_FF_RX_D_19(n80), .CH1_FF_RX_D_19(n81), + .CH0_FF_RX_D_20(n82), .CH1_FF_RX_D_20(n83), .CH0_FF_RX_D_21(n84), + .CH1_FF_RX_D_21(n85), .CH0_FF_RX_D_22(n86), .CH1_FF_RX_D_22(n87), + .CH0_FF_RX_D_23(n10), .CH1_FF_RX_D_23(n88), .CH0_FFS_PCIE_DONE(n11), + .CH1_FFS_PCIE_DONE(n89), .CH0_FFS_PCIE_CON(n12), .CH1_FFS_PCIE_CON(n90), + .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n91), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n92), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n93), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n94), + .CH0_FFS_RXFBFIFO_ERROR(n13), .CH1_FFS_RXFBFIFO_ERROR(n95), .CH0_FFS_TXFBFIFO_ERROR(n14), + .CH1_FFS_TXFBFIFO_ERROR(n96), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n97), + .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n98), .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n99), .CH0_LDR_RX2CORE(n100), .CH1_LDR_RX2CORE(_Z), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), - .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), - .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), - .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), - .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), - .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), - .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), - .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), - .D_REFCLKI(pll_refclki), .D_FFS_PLOL(pll_lol)) /* synthesis LOC=DCU1 CHAN=CH0 */ ; + .D_SCAN_OUT_0(n15), .D_SCAN_OUT_1(n16), .D_SCAN_OUT_2(n17), .D_SCAN_OUT_3(n18), + .D_SCAN_OUT_4(n19), .D_SCAN_OUT_5(n20), .D_SCAN_OUT_6(n21), .D_SCAN_OUT_7(n22), + .D_COUT0(n23), .D_COUT1(n24), .D_COUT2(n25), .D_COUT3(n26), + .D_COUT4(n27), .D_COUT5(n28), .D_COUT6(n29), .D_COUT7(n30), + .D_COUT8(n31), .D_COUT9(n32), .D_COUT10(n33), .D_COUT11(n34), + .D_COUT12(n35), .D_COUT13(n36), .D_COUT14(n37), .D_COUT15(n38), + .D_COUT16(n39), .D_COUT17(n40), .D_COUT18(n41), .D_COUT19(n42), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n45)) /* synthesis LOC=DCU1 CHAN=CH0 */ ; defparam DCU1_inst.D_MACROPDB = "0b1"; defparam DCU1_inst.D_IB_PWDNB = "0b1"; defparam DCU1_inst.D_XGE_MODE = "0b0"; @@ -185,7 +186,7 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, defparam DCU1_inst.CH0_RIO_MODE = "0b0"; defparam DCU1_inst.CH0_WA_MODE = "0b0"; defparam DCU1_inst.CH0_INVERT_RX = "0b0"; - defparam DCU1_inst.CH0_INVERT_TX = "0b0"; + defparam DCU1_inst.CH0_INVERT_TX = "0b1"; defparam DCU1_inst.CH0_PRBS_SELECTION = "0b0"; defparam DCU1_inst.CH0_GE_AN_ENABLE = "0b0"; defparam DCU1_inst.CH0_PRBS_LOCK = "0b0"; @@ -314,7 +315,7 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, defparam DCU1_inst.D_CMUSETBIASI = "0b00"; defparam DCU1_inst.D_SETPLLRC = "0d1"; defparam DCU1_inst.CH0_RX_RATE_SEL = "0d8"; - defparam DCU1_inst.D_REFCK_MODE = "0b100"; + defparam DCU1_inst.D_REFCK_MODE = "0b001"; defparam DCU1_inst.D_TX_VCO_CK_DIV = "0b010"; defparam DCU1_inst.D_PLL_LOL_SET = "0b00"; defparam DCU1_inst.D_RG_EN = "0b0"; @@ -361,7 +362,7 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n40 = 1'bz; assign n41 = 1'bz; assign n42 = 1'bz; - assign n43 = 1'bz; + assign n45 = 1'bz; assign n46 = 1'bz; assign n47 = 1'bz; assign n48 = 1'bz; @@ -417,19 +418,18 @@ module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n98 = 1'bz; assign n99 = 1'bz; assign n100 = 1'bz; - assign n101 = 1'bz; assign _Z = 1'bz; sgmii2sll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), - .slo_plol()); + .slo_plol(pll_lol)); defparam sll_inst.PPROTOCOL = "GBE"; defparam sll_inst.PLOL_SETTING = 0; defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; defparam sll_inst.PPCIE_MAX_RATE = "2.5"; - defparam sll_inst.PDIFF_VAL_LOCK = 98; - defparam sll_inst.PDIFF_VAL_UNLOCK = 196; - defparam sll_inst.PPCLK_TC = 327680; + defparam sll_inst.PDIFF_VAL_LOCK = 20; + defparam sll_inst.PDIFF_VAL_UNLOCK = 40; + defparam sll_inst.PPCLK_TC = 65536; defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; defparam sll_inst.PPCLK_DIV11_TC = 0; diff --git a/clarity/pcs/sgmii3/sgmii3.fdc b/clarity/pcs/sgmii3/sgmii3.fdc index 5424a21..6fbcac9 100644 --- a/clarity/pcs/sgmii3/sgmii3.fdc +++ b/clarity/pcs/sgmii3/sgmii3.fdc @@ -1,3 +1,2 @@ -###==== Start Generation +###==== Start Configuration -define_attribute {i:Lane0} {loc} {DCU1_CH1} diff --git a/clarity/pcs/sgmii3/sgmii3.lpc b/clarity/pcs/sgmii3/sgmii3.lpc index fc45681..53e7c43 100644 --- a/clarity/pcs/sgmii3/sgmii3.lpc +++ b/clarity/pcs/sgmii3/sgmii3.lpc @@ -11,11 +11,11 @@ CoreName=PCS CoreRevision=8.2 CoreStatus=Demo CoreType=LPM -Date=03/15/2019 +Date=03/21/2020 ModuleName=sgmii3 ParameterFileVersion=1.0 SourceFormat=verilog -Time=18:46:48 +Time=21:49:26 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -25,8 +25,8 @@ VendorName=Lattice Semiconductor Corporation CDRLOLACTION=Full Recalibration CDRLOLRANGE=0 CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 +CDR_MULT=10X +CDR_REF_RATE=125.0000 CH_MODE=Rx and Tx Destination=Synplicity EDIF=1 @@ -44,7 +44,7 @@ PROTOCOL=GbE PWAIT_RX_RDY=3000 PWAIT_TX_RDY=3000 RCSRC=Disabled -REFCLK_RATE=50.0000 +REFCLK_RATE=125.0000 RSTSEQSEL=Disabled RX8B10B=Enabled RXCOMMAA=1010000011 @@ -80,7 +80,7 @@ TXFIFO_ENABLE=Enabled TXINVPOL=Non-invert TXLDR=Off TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X +TXPLLMULT=10X TX_DATA_WIDTH=8/10-Bit TX_FICLK_RATE=125.0000 TX_LINE_RATE=1.2500 diff --git a/clarity/pcs/sgmii3/sgmii3.v b/clarity/pcs/sgmii3/sgmii3.v index 4f1eefe..fc55bf8 100644 --- a/clarity/pcs/sgmii3/sgmii3.v +++ b/clarity/pcs/sgmii3/sgmii3.v @@ -1,12 +1,12 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 -// Netlist written on Fri Mar 15 18:48:22 2019 +// Verilog netlist produced by program ASBGen: Ports rev. 2.32, Attr. rev. 2.70 +// Netlist written on Sat Mar 21 21:49:34 2020 // // Verilog Description of module sgmii3 // `timescale 1ns/1ps module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, - tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + tx_pclk, txi_clk, tx_full_clk, txdata, tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, @@ -21,6 +21,7 @@ module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, input rxrefclk; output tx_pclk; input txi_clk; + output tx_full_clk; input [7:0]txdata; input [0:0]tx_k; input [0:0]xmit; @@ -64,19 +65,19 @@ module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, - n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n42, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, - n94, n95, n96, n97, n98, n99, n100, n101, _Z; + n94, n95, n96, n97, n98, n99, n100, _Z; DCUA DCU1_inst (.CH0_HDINP(1'b0), .CH1_HDINP(hdinp), .CH0_HDINN(1'b0), .CH1_HDINN(hdinn), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(1'b0), .CH1_RX_REFCLK(rxrefclk), .CH0_FF_RXI_CLK(1'b1), .CH1_FF_RXI_CLK(tx_pclk), .CH0_FF_TXI_CLK(1'b1), .CH1_FF_TXI_CLK(txi_clk), .CH0_FF_EBRD_CLK(1'b1), - .CH1_FF_EBRD_CLK(tx_pclk), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), + .CH1_FF_EBRD_CLK(tx_full_clk), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), .CH0_FF_TX_D_1(1'b0), .CH1_FF_TX_D_1(txdata[1]), .CH0_FF_TX_D_2(1'b0), .CH1_FF_TX_D_2(txdata[2]), .CH0_FF_TX_D_3(1'b0), .CH1_FF_TX_D_3(txdata[3]), .CH0_FF_TX_D_4(1'b0), .CH1_FF_TX_D_4(txdata[4]), .CH0_FF_TX_D_5(1'b0), @@ -123,48 +124,48 @@ module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), - .D_CIN11(1'b0), .CH0_HDOUTP(n47), .CH1_HDOUTP(hdoutp), .CH0_HDOUTN(n48), + .D_CIN11(1'b0), .CH0_HDOUTP(n46), .CH1_HDOUTP(hdoutp), .CH0_HDOUTN(n47), .CH1_HDOUTN(hdoutn), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), - .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n49), - .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n50), .CH1_FF_RX_H_CLK(n6), - .CH0_FF_TX_F_CLK(n51), .CH1_FF_TX_F_CLK(n7), .CH0_FF_TX_H_CLK(n52), - .CH1_FF_TX_H_CLK(n8), .CH0_FF_RX_PCLK(n53), .CH1_FF_RX_PCLK(n9), - .CH0_FF_TX_PCLK(n54), .CH1_FF_TX_PCLK(tx_pclk), .CH0_FF_RX_D_0(n55), - .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n56), .CH1_FF_RX_D_1(rxdata[1]), - .CH0_FF_RX_D_2(n57), .CH1_FF_RX_D_2(rxdata[2]), .CH0_FF_RX_D_3(n58), - .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n59), .CH1_FF_RX_D_4(rxdata[4]), - .CH0_FF_RX_D_5(n60), .CH1_FF_RX_D_5(rxdata[5]), .CH0_FF_RX_D_6(n61), - .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n62), .CH1_FF_RX_D_7(rxdata[7]), - .CH0_FF_RX_D_8(n63), .CH1_FF_RX_D_8(rx_k[0]), .CH0_FF_RX_D_9(n64), - .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n65), .CH1_FF_RX_D_10(rx_cv_err[0]), - .CH0_FF_RX_D_11(n66), .CH1_FF_RX_D_11(n10), .CH0_FF_RX_D_12(n67), - .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), - .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), - .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), - .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), - .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), - .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), - .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), - .CH0_FF_RX_D_23(n89), .CH1_FF_RX_D_23(n11), .CH0_FFS_PCIE_DONE(n90), - .CH1_FFS_PCIE_DONE(n12), .CH0_FFS_PCIE_CON(n91), .CH1_FFS_PCIE_CON(n13), - .CH0_FFS_RLOS(n92), .CH1_FFS_RLOS(rx_los_low_s), .CH0_FFS_LS_SYNC_STATUS(n93), - .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), .CH0_FFS_CC_UNDERRUN(n94), - .CH1_FFS_CC_UNDERRUN(ctc_urun_s), .CH0_FFS_CC_OVERRUN(n95), .CH1_FFS_CC_OVERRUN(ctc_orun_s), - .CH0_FFS_RXFBFIFO_ERROR(n96), .CH1_FFS_RXFBFIFO_ERROR(n14), .CH0_FFS_TXFBFIFO_ERROR(n97), - .CH1_FFS_TXFBFIFO_ERROR(n15), .CH0_FFS_RLOL(n98), .CH1_FFS_RLOL(rx_cdr_lol_s), - .CH0_FFS_SKP_ADDED(n99), .CH1_FFS_SKP_ADDED(ctc_ins_s), .CH0_FFS_SKP_DELETED(n100), - .CH1_FFS_SKP_DELETED(ctc_del_s), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n48), + .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n49), .CH1_FF_RX_H_CLK(n6), + .CH0_FF_TX_F_CLK(n50), .CH1_FF_TX_F_CLK(tx_full_clk), .CH0_FF_TX_H_CLK(n51), + .CH1_FF_TX_H_CLK(n7), .CH0_FF_RX_PCLK(n52), .CH1_FF_RX_PCLK(n8), + .CH0_FF_TX_PCLK(n53), .CH1_FF_TX_PCLK(tx_pclk), .CH0_FF_RX_D_0(n54), + .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n55), .CH1_FF_RX_D_1(rxdata[1]), + .CH0_FF_RX_D_2(n56), .CH1_FF_RX_D_2(rxdata[2]), .CH0_FF_RX_D_3(n57), + .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n58), .CH1_FF_RX_D_4(rxdata[4]), + .CH0_FF_RX_D_5(n59), .CH1_FF_RX_D_5(rxdata[5]), .CH0_FF_RX_D_6(n60), + .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n61), .CH1_FF_RX_D_7(rxdata[7]), + .CH0_FF_RX_D_8(n62), .CH1_FF_RX_D_8(rx_k[0]), .CH0_FF_RX_D_9(n63), + .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n64), .CH1_FF_RX_D_10(rx_cv_err[0]), + .CH0_FF_RX_D_11(n65), .CH1_FF_RX_D_11(n9), .CH0_FF_RX_D_12(n66), + .CH1_FF_RX_D_12(n67), .CH0_FF_RX_D_13(n68), .CH1_FF_RX_D_13(n69), + .CH0_FF_RX_D_14(n70), .CH1_FF_RX_D_14(n71), .CH0_FF_RX_D_15(n72), + .CH1_FF_RX_D_15(n73), .CH0_FF_RX_D_16(n74), .CH1_FF_RX_D_16(n75), + .CH0_FF_RX_D_17(n76), .CH1_FF_RX_D_17(n77), .CH0_FF_RX_D_18(n78), + .CH1_FF_RX_D_18(n79), .CH0_FF_RX_D_19(n80), .CH1_FF_RX_D_19(n81), + .CH0_FF_RX_D_20(n82), .CH1_FF_RX_D_20(n83), .CH0_FF_RX_D_21(n84), + .CH1_FF_RX_D_21(n85), .CH0_FF_RX_D_22(n86), .CH1_FF_RX_D_22(n87), + .CH0_FF_RX_D_23(n88), .CH1_FF_RX_D_23(n10), .CH0_FFS_PCIE_DONE(n89), + .CH1_FFS_PCIE_DONE(n11), .CH0_FFS_PCIE_CON(n90), .CH1_FFS_PCIE_CON(n12), + .CH0_FFS_RLOS(n91), .CH1_FFS_RLOS(rx_los_low_s), .CH0_FFS_LS_SYNC_STATUS(n92), + .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), .CH0_FFS_CC_UNDERRUN(n93), + .CH1_FFS_CC_UNDERRUN(ctc_urun_s), .CH0_FFS_CC_OVERRUN(n94), .CH1_FFS_CC_OVERRUN(ctc_orun_s), + .CH0_FFS_RXFBFIFO_ERROR(n95), .CH1_FFS_RXFBFIFO_ERROR(n13), .CH0_FFS_TXFBFIFO_ERROR(n96), + .CH1_FFS_TXFBFIFO_ERROR(n14), .CH0_FFS_RLOL(n97), .CH1_FFS_RLOL(rx_cdr_lol_s), + .CH0_FFS_SKP_ADDED(n98), .CH1_FFS_SKP_ADDED(ctc_ins_s), .CH0_FFS_SKP_DELETED(n99), + .CH1_FFS_SKP_DELETED(ctc_del_s), .CH0_LDR_RX2CORE(n100), .CH1_LDR_RX2CORE(_Z), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), - .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), - .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), - .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), - .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), - .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), - .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), - .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), - .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n46)) /* synthesis LOC=DCU1 CHAN=CH1 */ ; + .D_SCAN_OUT_0(n15), .D_SCAN_OUT_1(n16), .D_SCAN_OUT_2(n17), .D_SCAN_OUT_3(n18), + .D_SCAN_OUT_4(n19), .D_SCAN_OUT_5(n20), .D_SCAN_OUT_6(n21), .D_SCAN_OUT_7(n22), + .D_COUT0(n23), .D_COUT1(n24), .D_COUT2(n25), .D_COUT3(n26), + .D_COUT4(n27), .D_COUT5(n28), .D_COUT6(n29), .D_COUT7(n30), + .D_COUT8(n31), .D_COUT9(n32), .D_COUT10(n33), .D_COUT11(n34), + .D_COUT12(n35), .D_COUT13(n36), .D_COUT14(n37), .D_COUT15(n38), + .D_COUT16(n39), .D_COUT17(n40), .D_COUT18(n41), .D_COUT19(n42), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n45)) /* synthesis LOC=DCU1 CHAN=CH1 */ ; defparam DCU1_inst.D_MACROPDB = "0b1"; defparam DCU1_inst.D_IB_PWDNB = "0b1"; defparam DCU1_inst.D_XGE_MODE = "0b0"; @@ -312,7 +313,7 @@ module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, defparam DCU1_inst.D_CMUSETBIASI = "0b00"; defparam DCU1_inst.D_SETPLLRC = "0d1"; defparam DCU1_inst.CH1_RX_RATE_SEL = "0d8"; - defparam DCU1_inst.D_REFCK_MODE = "0b100"; + defparam DCU1_inst.D_REFCK_MODE = "0b001"; defparam DCU1_inst.D_TX_VCO_CK_DIV = "0b010"; defparam DCU1_inst.D_PLL_LOL_SET = "0b00"; defparam DCU1_inst.D_RG_EN = "0b0"; @@ -359,7 +360,7 @@ module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n40 = 1'bz; assign n41 = 1'bz; assign n42 = 1'bz; - assign n43 = 1'bz; + assign n45 = 1'bz; assign n46 = 1'bz; assign n47 = 1'bz; assign n48 = 1'bz; @@ -415,7 +416,6 @@ module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n98 = 1'bz; assign n99 = 1'bz; assign n100 = 1'bz; - assign n101 = 1'bz; assign _Z = 1'bz; endmodule |
