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authormindchasers <privateisland@mindchasers.com>2019-07-08 19:54:17 -0400
committermindchasers <privateisland@mindchasers.com>2019-07-08 19:54:17 -0400
commitbbe7e48ee202c2e1075ea6a69733d030b8bf3ddf (patch)
treec4cecd733140d94d19c40e08c74e50de16cce389 /boards/darsena/labs.rvl
parentde26fff172b7b3d2019c2ab52ab0c98536e461d4 (diff)
ldf: update project file to include reveal files for lab exercises
also update .gitignore and prune boards directory to remove *.trc from repo since it's not a source file.
Diffstat (limited to 'boards/darsena/labs.rvl')
0 files changed, 0 insertions, 0 deletions

Highly Recommended Verilog Books