diff options
Diffstat (limited to 'ml_module_agilex3.kicad_pro')
| -rw-r--r-- | ml_module_agilex3.kicad_pro | 114 |
1 files changed, 88 insertions, 26 deletions
diff --git a/ml_module_agilex3.kicad_pro b/ml_module_agilex3.kicad_pro index 095a30e..c810344 100644 --- a/ml_module_agilex3.kicad_pro +++ b/ml_module_agilex3.kicad_pro @@ -61,7 +61,7 @@ "hatch_smoothing_value": 0.1, "hatch_thickness": 1.0, "min_clearance": 0.5, - "min_island_area": 10.0, + "min_island_area": 9.9999993548, "min_thickness": 0.25, "pad_connection": 1, "remove_islands": 0, @@ -69,7 +69,13 @@ "thermal_relief_spoke_width": 0.5 } }, - "diff_pair_dimensions": [], + "diff_pair_dimensions": [ + { + "gap": 0.0, + "via_gap": 0.0, + "width": 0.0 + } + ], "drc_exclusions": [], "meta": { "version": 2 @@ -110,9 +116,9 @@ "missing_tuning_profile": "warning", "net_conflict": "warning", "nonmirrored_text_on_back_layer": "warning", - "npth_inside_courtyard": "error", + "npth_inside_courtyard": "ignore", "padstack": "warning", - "pth_inside_courtyard": "error", + "pth_inside_courtyard": "ignore", "shorting_items": "error", "silk_edge_clearance": "warning", "silk_over_copper": "warning", @@ -144,7 +150,7 @@ "min_connection": 0.0, "min_copper_edge_clearance": 0.5, "min_groove_width": 0.0, - "min_hole_clearance": 0.25, + "min_hole_clearance": 0.3, "min_hole_to_hole": 0.25, "min_microvia_diameter": 0.2, "min_microvia_drill": 0.1, @@ -152,11 +158,11 @@ "min_silk_clearance": 0.0, "min_text_height": 0.8, "min_text_thickness": 0.08, - "min_through_hole_diameter": 0.3, - "min_track_width": 0.2, - "min_via_annular_width": 0.1, + "min_through_hole_diameter": 0.15, + "min_track_width": 0.0, + "min_via_annular_width": 0.125, "min_via_diameter": 0.5, - "solder_mask_to_copper_clearance": 0.0, + "solder_mask_to_copper_clearance": 0.03, "use_height_for_length_calcs": true }, "teardrop_options": [ @@ -203,7 +209,13 @@ "td_width_to_size_filter_ratio": 0.9 } ], - "track_widths": [], + "track_widths": [ + 0.0, + 0.1, + 0.125, + 0.2, + 0.5 + ], "tuning_pattern_settings": { "diff_pair_defaults": { "corner_radius_percentage": 80, @@ -230,7 +242,16 @@ "spacing": 0.6 } }, - "via_dimensions": [], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + }, + { + "diameter": 0.45, + "drill": 0.2 + } + ], "zones_allow_external_fillets": false }, "ipc2581": { @@ -495,7 +516,7 @@ "classes": [ { "bus_width": 12, - "clearance": 0.2, + "clearance": 0.1, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, @@ -506,6 +527,42 @@ "pcb_color": "rgba(0, 0, 0, 0.000)", "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.1, + "tuning_profile": "", + "via_diameter": 0.6, + "via_drill": 0.3, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.1, + "diff_pair_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "All Nets", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.1, + "tuning_profile": "", + "via_diameter": 0.6, + "via_drill": 0.3, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Power", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, + "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.2, "tuning_profile": "", "via_diameter": 0.6, @@ -518,7 +575,12 @@ }, "net_colors": null, "netclass_assignments": null, - "netclass_patterns": [] + "netclass_patterns": [ + { + "netclass": "Power", + "pattern": "V3_3" + } + ] }, "pcbnew": { "last_paths": { @@ -663,23 +725,23 @@ "uuid": "40f68d6b-1137-4ac8-b168-b5b95c774b2e" }, { - "filename": "fpga_banks_3a_6a.kicad_sch", - "name": "FPGA Banks 3A and 6A", + "filename": "fpga_banks_6a_6b.kicad_sch", + "name": "FPGA Banks 6A and 6B", "uuid": "3c0900d6-fd44-4d2a-8ed4-61ac6016b344" }, { - "filename": "fpga_banks_6b_6c.kicad_sch", - "name": "FPGA Banks 6B and 6C", + "filename": "fpga_banks_6c_6d.kicad_sch", + "name": "FPGA Banks 6C and 6D", "uuid": "0e7c7e5f-82cf-4601-92b9-defcfbaad9a6" }, { - "filename": "fpga_banks_6d_6e.kicad_sch", - "name": "FPGA Banks 6D and 6E", + "filename": "fpga_banks_6e_6f.kicad_sch", + "name": "FPGA Banks 6E and 6F", "uuid": "1c3aedd9-9d83-472c-a6eb-08aa4aa51563" }, { - "filename": "fpga_banks_6f_6g_6h.kicad_sch", - "name": "FPGA Banks 6F, 6G and 6H", + "filename": "fpga_banks_6g_6h.kicad_sch", + "name": "FPGA Banks 6G and 6H", "uuid": "40dd6d9b-cedf-466e-93c7-0250310dbdfa" }, { @@ -688,7 +750,7 @@ "uuid": "47d203e8-6013-4021-be29-15e7a1672177" } ], - "used_designators": "U4", + "used_designators": "", "variants": [] }, "sheets": [ @@ -710,19 +772,19 @@ ], [ "3c0900d6-fd44-4d2a-8ed4-61ac6016b344", - "FPGA Banks 3A and 6A" + "FPGA Banks 6A and 6B" ], [ "0e7c7e5f-82cf-4601-92b9-defcfbaad9a6", - "FPGA Banks 6B and 6C" + "FPGA Banks 6C and 6D" ], [ "1c3aedd9-9d83-472c-a6eb-08aa4aa51563", - "FPGA Banks 6D and 6E" + "FPGA Banks 6E and 6F" ], [ "40dd6d9b-cedf-466e-93c7-0250310dbdfa", - "FPGA Banks 6F, 6G and 6H" + "FPGA Banks 6G and 6H" ], [ "47d203e8-6013-4021-be29-15e7a1672177", |
