aboutsummaryrefslogtreecommitdiffhomepage
path: root/sim/.gitignore
blob: 2c89c7f34611b2525ecb1f4b4fafcf2516eb6c46 (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13

aldec/
synopsys/
xcelium/
libraries/
work/
rtl_work/
vsim.wlf
wlf*
transcript
*.mti
*.orig
*.bak
msim_transcript
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-05-24 15:48:32 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis