initial commit, see README in top folderHEADmaster

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diff --git a/src/ml_module_agilex.v b/src/ml_module_agilex.v
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+
+/*
+ *   ml_module_agilex.v
+ *
+ *   Copyright (C) 2026 Private Island Networks Inc.
+ *       
+ *   Licensed under the Apache License, Version 2.0 (the "License");
+ *   you may not use this file except in compliance with the License.
+ *   You may obtain a copy of the License at
+ *
+ *       http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *   Unless required by applicable law or agreed to in writing, software
+ *   distributed under the License is distributed on an "AS IS" BASIS,
+ *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *   See the License for the specific language governing permissions and
+ *   limitations under the License.
+ *       
+ *	 function: top module for Machine Learning Module using Agilex 3
+ *	 
+ *	 
+ */ 
+
+module  ml_module_agilex (
+	input rstn,
+	input clk_i,			// 25Mhz input
+		
+`ifdef SIMULATION
+	output pll_locked_o,
+	output pclk,			// primary clock
+`endif
+		
+	// RGMII PHY Emulation, Module GigE Interface
+	input rgmii_rx_clk,
+	input rgmii_rx_ctl,
+	input [3:0] rgmii_rx_d,
+	
+	output rgmii_tx_clk,
+	output rgmii_tx_ctl,
+	output [3:0] rgmii_tx_d,
+	
+	input rgmii_mdc,
+	inout rgmii_mdio,
+	
+	output rgmii_intn,		
+	output [1:0] rgmii_gpio,
+	
+	// Alternate High Speed LVDS Interface
+	
+	// Configuration ROM / FLASH (Xccela) Interface
+	output flash_clk,
+	input flash_dqs,
+	output flash_seln,
+	inout [7:0] flash_d,
+	
+	// Optional LPDDR4 Exernal DDR Memory
+	
+	// Optional LVDS SMA Interface
+	
+	// Optional GPIO External Connector for Expansion
+	
+	// Debug
+	output [2:0] fpga_led
+);
+
+wire [1:0] tx_ctl, rx_ctl;
+wire [7:0] tx_d, rx_d;
+
+pll_io pll_0(
+	.refclk(clk_i),   			//  refclk.clk,    The reference clock source that drives the I/O PLL.
+	.locked(pll_locked_o),   	//  locked.export, The IOPLL IP core drives this port high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock.
+	.rst(~rstn),      			//   reset.reset,  The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.
+	.outclk_0(clk_25), 			// outclk0.clk,    Output clock Channel 0 from I/O PLL.
+	.outclk_1(clk_125)  			// outclk1.clk,    Output clock Channel 1 from I/O PLL.
+);
+
+ddr_i rgmii_i (
+	.ck(rgmii_rx_clk), 
+	.dout({{rx_ctl[1],rx_d[7:4]},{rx_ctl[0],rx_d[3:0]}}),	
+	.pad_in({rgmii_rx_ctl, rgmii_rx_d})
+);
+
+// Simple loopback
+assign tx_ctl = rx_ctl;
+assign tx_d = rx_d;
+	
+ddr_o rgmii_o(
+	.ck(clk_125),    
+	.din({{1'b0, tx_ctl[1], tx_d[7:4]},{1'b1, tx_ctl[0], tx_d[3:0]}}),  
+	.pad_out({rgmii_tx_clk, rgmii_tx_ctl, rgmii_tx_d}) 
+);
+	
+assign fpga_led = 3'b101;
+
+	
+endmodule