Overview
The Private Island Explorer (PI-EXP) Web Server provides a browser based user interface (UI) to a Private Island FPGA-based (PI) node via an Ethernet LAN. The server is intentionally light weight and currently relies on the aiohttp Web framework to serve pages to a browser and also exchange information via a WebSocket interface. This in-progress article describes the goals, features, usage, dependencies, and design of the project.
The opens source PI-EXP Python project can be cloned from our local Git server.
Overview
The PI-EXP project is developed with Python and various Web technologies, such as JavaScript, HTML, and CSS. The Web server relies on the aiohttp Web framework to serve HTML pages and provide other core Web server support, such as template and context processing.
The Python PyShark library and tshark network traffic analyzer are utilized to capture responses from the embedded soft controller and automated messages generated from blocks like the Machine Learning Engine (MLE).
The figure below depicts how the PI-EXP server interfaces with a PI Node. The user interface is provided via the browswer and enables the user to send queries via the LAN to the controller for various purposes and also receive packets / messages that are triggered automatically depending on how the PI node is configured.
PI-EXP Views
The sections below explain the various views provided by the PI-EXP UI. Note that these are all in various stages of development.
Home
Stage: concept
Provides overall status of PI node and a graphical, interactive view of the internal PI modules within the FPGA. Supports clicking on modules and redirecting to the associated UI view.
Controller
Stage: prototype
Use this view to send individual read and write messages via the LAN to the controller. Note that accessing certain addressable space can trigger additional action, such as accessing MDIO registers within an Ethernet PHY.
Machine Learning Engine
Stage: concept
This view currently logs vectors (packets) generated by the MLE. Future uses of this view may be to integrate inferencing and its results.
MDIO
Stage: prototype
This view currently performs a quick scan of the Ethernet PHY's internal registers via its MDIO interface. Refer to the PHY's datasheet for the definition of each register.
Note that at the time of testing this feature there is an address skew in the registers by one. This appears to be in the FPGA image and requires further investigation.
Switch Fabric
Stage: not started
