summaryrefslogtreecommitdiffhomepage
path: root/manufacturer/altera
AgeCommit message (Expand)Author
3 dayssim: upddate mpf project file, tb, and sim scripts to support first pass pkt_genpkt_genPrivate Island Networks Inc
3 dayspkt_gen: create first pass skelton source file and changes to support packet ...Private Island Networks Inc
4 dayssim: update sim related files for website article https://privateisland.tech/...HEADmasterPrivate Island Networks Inc
2026-02-03mle: patch files to support FSM3, MLE header, and bug fixesPrivate Island Networks Inc
2025-12-21betsy: preliminary beta snapshotPrivate Island Networks Inc
2025-07-03manu: prune and rename to make currentdarsenaPrivate Island Networks
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-07-03 21:32:30 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis