diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cont_params.v | 5 | ||||
| -rw-r--r-- | src/controller.v | 8 | ||||
| -rw-r--r-- | src/pkt_gen.v | 80 |
3 files changed, 89 insertions, 4 deletions
diff --git a/src/cont_params.v b/src/cont_params.v index c9f85c2..d871534 100644 --- a/src/cont_params.v +++ b/src/cont_params.v @@ -40,15 +40,14 @@ localparam MSG_TYPE_REPLY_SUCCESS = 8'h3; localparam MSG_TYPE_REPLY_ERROR = 8'h4; localparam MSG_TYPE_NOTIY = 8'h5; - localparam MSG_CONTROLLER_ADDR = 16'h0000; localparam MSG_MAC_ADDR = 16'h0100; localparam MSG_PKT_FILTER_ADDR = 16'h0200; localparam MSG_SWITCH_ADDR = 16'h0500; localparam MSG_MDIO_ADDR = 16'h0600; localparam MSG_MLE_ADDR = 16'h0700; -localparam MSG_INVALID_ADDR = 16'h0800; - +localparam MSG_PKT_GEN_ADDR = 16'h0800; +localparam MSG_INVALID_ADDR = 16'h0900; localparam HF_TX_WR_PTR_ADDR = 16'd0; localparam HF_TX_RD_PTR_ADDR = 16'd1; // read only diff --git a/src/controller.v b/src/controller.v index e30d461..922a9f0 100644 --- a/src/controller.v +++ b/src/controller.v @@ -48,6 +48,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) output reg pkt_filter_sel, output reg mac_sel, output reg mle_sel, + output reg pkt_gen_sel, output reg hf_ptrs_sel, output reg hf_tx_sel, output reg hf_rx_sel, @@ -341,6 +342,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) {MSG_MAC_ADDR[15:8],8'h??}: msg_response <= mem_d_i; {MSG_MDIO_ADDR[15:8],8'h??}: msg_response <= mdio_d; {MSG_MLE_ADDR[15:8],8'h??}: msg_response <= mem_d_i; + {MSG_PKT_GEN_ADDR[15:8],8'h??}: msg_response <= mem_d_i; default: msg_response <= mem_d_i[15:0]; endcase @@ -486,7 +488,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) mem_cmd <= 1'b0; else if (cont_state == CONT_ST_IDLE && !rx_msg_captured) mem_cmd <= 1'b0; - else if (rx_msg_captured && msg_addr[15:8] >= MSG_MAC_ADDR[15:8] && msg_addr[15:8] < MSG_MLE_ADDR[15:8]) + else if (rx_msg_captured && msg_addr[15:8] >= MSG_MAC_ADDR[15:8] && msg_addr[15:8] < MSG_INVALID_ADDR[15:8]) mem_cmd <= 1'b1; // Primary Memory Controller Actions @@ -498,6 +500,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) mac_sel <= 1'b0; mle_sel <= 1'b0; pkt_filter_sel <= 1'b0; + pkt_gen_sel <= 1'b0; hf_ptrs_sel <= 1'b0; hf_tx_sel <= 1'b0; hf_rx_sel <= 1'b0; @@ -534,6 +537,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) MSG_MAC_ADDR[15:8]: mac_sel <= 1'b1; MSG_PKT_FILTER_ADDR[15:8]: pkt_filter_sel <= 1'b1; MSG_MLE_ADDR[15:8]: mle_sel <= 1'b1; + MSG_PKT_GEN_ADDR[15:8]: pkt_gen_sel <= 1'b1; endcase end end @@ -544,6 +548,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) mac_sel <= 1'b0; mle_sel <= 1'b0; pkt_filter_sel <= 1'b0; + pkt_gen_sel <= 1'b0; end else if (mem_state == MEM_ST_REPLY_START && tx_fifo_empty) begin // write byte cnt hf_ptrs_sel <= 1'b1; @@ -606,6 +611,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) hf_ptrs_sel <= 1'b0; hf_tx_sel <= 1'b0; hf_rx_sel <= 1'b0; + pkt_gen_sel <= 1'b0; end // rx_cnt diff --git a/src/pkt_gen.v b/src/pkt_gen.v new file mode 100644 index 0000000..819322d --- /dev/null +++ b/src/pkt_gen.v @@ -0,0 +1,80 @@ +/* + * pkt_gen.v + * + * Copyright (C) 2026 Private Island Networks Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * function: programmable packet generator + * + * see https://privateisland.tech/dev/pi-pkt-gen + * + */ + +module pkt_gen #(parameter DEPTH = 8, parameter DATAW = 16) +( + input rstn, + input pclk, + + // controller interface + input cont_clk, + input cont_sel, + input cont_we, + input [$clog2(DEPTH)-1:0] cont_addr, + input [DATAW-1:0] cont_d_i, + output reg [DATAW-1:0] cont_d_o, + output cont_tgt_ready, + + // switch interface + output fifo_empty_o, + input fifo_re, + output [8:0] fifo_d_o, + output [10:0] byte_cnt +); + + /*** local params ***/ + + localparam PKT_GEN_ENABLE_ADDR = 'h0; + + /*** variables ***/ + reg pkt_gen_en; + + /*** logic ***/ + + // mle_enable: enable / disable the MLE + always @(posedge cont_clk, negedge rstn) + if (!rstn) + pkt_gen_en <= 1'b0; + else if (cont_we && cont_sel && cont_addr == PKT_GEN_ENABLE_ADDR) + pkt_gen_en <= cont_d_i[0]; + + // Controller Read Data Mux + always @(posedge cont_clk, negedge rstn) + if (!rstn) + cont_d_o <= 16'hcccc; + else + case (cont_addr) + PKT_GEN_ENABLE_ADDR: cont_d_o <= pkt_gen_en; + default: cont_d_o <= cont_d_o; + endcase + + // tie offs for now + assign cont_tgt_ready = 1'b1; + assign fifo_empty_o = 1'b0; + assign fifo_d_o = 9'h1ff; + assign byte_cnt = 'd0; + + + +endmodule + |
