diff options
Diffstat (limited to 'src/controller.v')
| -rw-r--r-- | src/controller.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/controller.v b/src/controller.v index e30d461..922a9f0 100644 --- a/src/controller.v +++ b/src/controller.v @@ -48,6 +48,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) output reg pkt_filter_sel, output reg mac_sel, output reg mle_sel, + output reg pkt_gen_sel, output reg hf_ptrs_sel, output reg hf_tx_sel, output reg hf_rx_sel, @@ -341,6 +342,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) {MSG_MAC_ADDR[15:8],8'h??}: msg_response <= mem_d_i; {MSG_MDIO_ADDR[15:8],8'h??}: msg_response <= mdio_d; {MSG_MLE_ADDR[15:8],8'h??}: msg_response <= mem_d_i; + {MSG_PKT_GEN_ADDR[15:8],8'h??}: msg_response <= mem_d_i; default: msg_response <= mem_d_i[15:0]; endcase @@ -486,7 +488,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) mem_cmd <= 1'b0; else if (cont_state == CONT_ST_IDLE && !rx_msg_captured) mem_cmd <= 1'b0; - else if (rx_msg_captured && msg_addr[15:8] >= MSG_MAC_ADDR[15:8] && msg_addr[15:8] < MSG_MLE_ADDR[15:8]) + else if (rx_msg_captured && msg_addr[15:8] >= MSG_MAC_ADDR[15:8] && msg_addr[15:8] < MSG_INVALID_ADDR[15:8]) mem_cmd <= 1'b1; // Primary Memory Controller Actions @@ -498,6 +500,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) mac_sel <= 1'b0; mle_sel <= 1'b0; pkt_filter_sel <= 1'b0; + pkt_gen_sel <= 1'b0; hf_ptrs_sel <= 1'b0; hf_tx_sel <= 1'b0; hf_rx_sel <= 1'b0; @@ -534,6 +537,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) MSG_MAC_ADDR[15:8]: mac_sel <= 1'b1; MSG_PKT_FILTER_ADDR[15:8]: pkt_filter_sel <= 1'b1; MSG_MLE_ADDR[15:8]: mle_sel <= 1'b1; + MSG_PKT_GEN_ADDR[15:8]: pkt_gen_sel <= 1'b1; endcase end end @@ -544,6 +548,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) mac_sel <= 1'b0; mle_sel <= 1'b0; pkt_filter_sel <= 1'b0; + pkt_gen_sel <= 1'b0; end else if (mem_state == MEM_ST_REPLY_START && tx_fifo_empty) begin // write byte cnt hf_ptrs_sel <= 1'b1; @@ -606,6 +611,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3) hf_ptrs_sel <= 1'b0; hf_tx_sel <= 1'b0; hf_rx_sel <= 1'b0; + pkt_gen_sel <= 1'b0; end // rx_cnt |
