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-rw-r--r--manufacturer/altera/cyclone10_lp/betsy.qsf67
-rw-r--r--manufacturer/altera/cyclone10_lp/src/betsy.v43
2 files changed, 66 insertions, 44 deletions
diff --git a/manufacturer/altera/cyclone10_lp/betsy.qsf b/manufacturer/altera/cyclone10_lp/betsy.qsf
index 2d4da4c..d110252 100644
--- a/manufacturer/altera/cyclone10_lp/betsy.qsf
+++ b/manufacturer/altera/cyclone10_lp/betsy.qsf
@@ -50,7 +50,7 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)"
+set_global_assignment -name EDA_SIMULATION_TOOL "QuestaSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
@@ -349,38 +349,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SDC_FILE betsy.sdc
-set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp
-set_global_assignment -name VERILOG_FILE src/betsy.v
-set_global_assignment -name VERILOG_FILE ../../../src/cam.v
-set_global_assignment -name VERILOG_FILE ../../../src/controller.v
-set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v
-set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v
-set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v
-set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v
-set_global_assignment -name VERILOG_FILE ../../../src/fcs.v
-set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v
-set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v
-set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v
-set_global_assignment -name VERILOG_FILE ../../../src/mdio.v
-set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v
-set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v
-set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v
-set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v
-set_global_assignment -name VERILOG_FILE ../../../src/rm.v
-set_global_assignment -name VERILOG_FILE ../../../src/switch.v
-set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v
-set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v
-set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v
-set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip
-set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip
-set_global_assignment -name QIP_FILE ip/pll/pll.qip
-set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip
-set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id tst_controller
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id tst_controller
@@ -738,5 +706,38 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id tst_controller
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id tst_controller
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id tst_controller
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/sim/win" -section_id eda_simulation
+set_global_assignment -name SDC_FILE betsy.sdc
+set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp
+set_global_assignment -name VERILOG_FILE src/betsy.v
+set_global_assignment -name VERILOG_FILE ../../../src/cam.v
+set_global_assignment -name VERILOG_FILE ../../../src/controller.v
+set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v
+set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v
+set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v
+set_global_assignment -name VERILOG_FILE ../../../src/fcs.v
+set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v
+set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v
+set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v
+set_global_assignment -name VERILOG_FILE ../../../src/mdio.v
+set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v
+set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v
+set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v
+set_global_assignment -name VERILOG_FILE ../../../src/pkt_gen.v
+set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v
+set_global_assignment -name VERILOG_FILE ../../../src/switch.v
+set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v
+set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v
+set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip
+set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip
+set_global_assignment -name QIP_FILE ip/pll/pll.qip
+set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip
+set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/betsy_auto_stripped.stp \ No newline at end of file
diff --git a/manufacturer/altera/cyclone10_lp/src/betsy.v b/manufacturer/altera/cyclone10_lp/src/betsy.v
index ccefd3b..75d419a 100644
--- a/manufacturer/altera/cyclone10_lp/src/betsy.v
+++ b/manufacturer/altera/cyclone10_lp/src/betsy.v
@@ -248,7 +248,7 @@ module betsy (
wire [NUM_PHYS-1:0] mode_100Mbit;
// Controller Peripheral Address Decode and Select
- wire mac_sel, pkt_filter_sel, mle_sel;
+ wire mac_sel, pkt_filter_sel, mle_sel, pkt_gen_sel;
wire [1:0] mac_addr;
wire [15:0] pkt_filter_addr;
@@ -291,8 +291,9 @@ module betsy (
wire [31:0] mem_d_o;
wire mem_we, mem_oe;
wire mem_tgt_ready, mem_tgt_ready_mac_0, mem_tgt_ready_mac_1;
+ wire mem_tgt_ready_mle, mem_tgt_ready_pkt_gen;
wire [15:0] mac_0_d_o, mac_1_d_o, mac_2_d_o;
- wire [15:0] mle_d_o;
+ wire [15:0] mle_d_o, pkt_gen_d_o;
wire [10:0] hfifo_d_o;
// half FIFO / Interface for Controller
@@ -523,6 +524,7 @@ module betsy (
.pkt_filter_sel(pkt_filter_sel),
.mac_sel(mac_sel),
.mle_sel(mle_sel),
+ .pkt_gen_sel(pkt_gen_sel),
.hf_ptrs_sel(hf_ptrs_sel),
.hf_rx_sel(hf_rx_sel),
.hf_tx_sel(hf_tx_sel),
@@ -551,18 +553,19 @@ module betsy (
);
- assign mem_tgt_ready = mem_tgt_ready_mac_0 && mem_tgt_ready_mac_1;
+ assign mem_tgt_ready = mem_tgt_ready_mac_0 | mem_tgt_ready_mac_1 | mem_tgt_ready_mle | mem_tgt_ready_pkt_gen;
// controller data mux
always @(*)
- casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, mle_sel, mac_sel, mac_addr})
- 7'b0000100: mem_d_i = {16'h0000, mac_0_d_o};
- 7'b0000101: mem_d_i = {16'h0000, mac_1_d_o};
- 7'b0000110: mem_d_i = {16'h0000, mac_2_d_o};
- 7'b00010??: mem_d_i = {16'h0000, mle_d_o};
- 7'b00100??: mem_d_i = {21'h0000, hfifo_d_o};
- 7'b01000??: mem_d_i = {21'h0000, hfifo_d_o};
- 7'b10000??: mem_d_i = {21'h0000, hfifo_d_o};
+ casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, pkt_gen_sel, mle_sel, mac_sel, mac_addr})
+ 8'b00000100: mem_d_i = {16'h0000, mac_0_d_o};
+ 8'b00000101: mem_d_i = {16'h0000, mac_1_d_o};
+ 8'b00000110: mem_d_i = {16'h0000, mac_2_d_o};
+ 8'b000010??: mem_d_i = {16'h0000, mle_d_o};
+ 8'b000100??: mem_d_i = {16'h0000, pkt_gen_d_o};
+ 8'b001000??: mem_d_i = {21'h0000, hfifo_d_o};
+ 8'b010000??: mem_d_i = {21'h0000, hfifo_d_o};
+ 8'b100000??: mem_d_i = {21'h0000, hfifo_d_o};
default: mem_d_i = 32'd0;
endcase
@@ -695,6 +698,24 @@ module betsy (
.fifo_d_o(mle_fifo_d_o),
.byte_cnt(rx_mle_byte_cnt)
);
+
+ pkt_gen pkt_gen_0(
+ .rstn(sys_rstn),
+ .pclk(pclk),
+ // controller interface
+ .cont_clk(cont_clk),
+ .cont_sel(pkt_gen_sel),
+ .cont_we(mem_we),
+ .cont_addr(mem_addr),
+ .cont_d_i(mem_d_o[15:0]),
+ .cont_d_o(pkt_gen_d_o),
+ .cont_tgt_ready(mem_tgt_ready_pkt_gen),
+ // switch interface
+ .fifo_empty_o(),
+ .fifo_re(1'b0),
+ .fifo_d_o(),
+ .byte_cnt()
+ );
/*
* Controls the routing of data and transmit modes
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-07-03 22:43:10 +0000

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