diff options
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/betsy.qsf')
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/betsy.qsf | 67 |
1 files changed, 34 insertions, 33 deletions
diff --git a/manufacturer/altera/cyclone10_lp/betsy.qsf b/manufacturer/altera/cyclone10_lp/betsy.qsf index 2d4da4c..d110252 100644 --- a/manufacturer/altera/cyclone10_lp/betsy.qsf +++ b/manufacturer/altera/cyclone10_lp/betsy.qsf @@ -50,7 +50,7 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)" +set_global_assignment -name EDA_SIMULATION_TOOL "QuestaSim (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing @@ -349,38 +349,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SDC_FILE betsy.sdc -set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp -set_global_assignment -name VERILOG_FILE src/betsy.v -set_global_assignment -name VERILOG_FILE ../../../src/cam.v -set_global_assignment -name VERILOG_FILE ../../../src/controller.v -set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v -set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v -set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v -set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v -set_global_assignment -name VERILOG_FILE ../../../src/fcs.v -set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v -set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v -set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v -set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v -set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v -set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v -set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v -set_global_assignment -name VERILOG_FILE ../../../src/mdio.v -set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v -set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v -set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v -set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v -set_global_assignment -name VERILOG_FILE ../../../src/rm.v -set_global_assignment -name VERILOG_FILE ../../../src/switch.v -set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v -set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v -set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v -set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip -set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip -set_global_assignment -name QIP_FILE ip/pll/pll.qip -set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip -set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id tst_controller set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id tst_controller @@ -738,5 +706,38 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE= set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id tst_controller set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id tst_controller set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id tst_controller +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/sim/win" -section_id eda_simulation +set_global_assignment -name SDC_FILE betsy.sdc +set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name VERILOG_FILE src/betsy.v +set_global_assignment -name VERILOG_FILE ../../../src/cam.v +set_global_assignment -name VERILOG_FILE ../../../src/controller.v +set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v +set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v +set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v +set_global_assignment -name VERILOG_FILE ../../../src/fcs.v +set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v +set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v +set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v +set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v +set_global_assignment -name VERILOG_FILE ../../../src/pkt_gen.v +set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v +set_global_assignment -name VERILOG_FILE ../../../src/switch.v +set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v +set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip +set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip +set_global_assignment -name QIP_FILE ip/pll/pll.qip +set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip +set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name SLD_FILE db/betsy_auto_stripped.stp
\ No newline at end of file |
