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-rw-r--r--manufacturer/altera/cyclone10_lp/betsy.qsf67
-rw-r--r--manufacturer/altera/cyclone10_lp/src/betsy.v43
-rw-r--r--src/cont_params.v5
-rw-r--r--src/controller.v8
-rw-r--r--src/pkt_gen.v80
5 files changed, 155 insertions, 48 deletions
diff --git a/manufacturer/altera/cyclone10_lp/betsy.qsf b/manufacturer/altera/cyclone10_lp/betsy.qsf
index 2d4da4c..d110252 100644
--- a/manufacturer/altera/cyclone10_lp/betsy.qsf
+++ b/manufacturer/altera/cyclone10_lp/betsy.qsf
@@ -50,7 +50,7 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)"
+set_global_assignment -name EDA_SIMULATION_TOOL "QuestaSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
@@ -349,38 +349,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SDC_FILE betsy.sdc
-set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp
-set_global_assignment -name VERILOG_FILE src/betsy.v
-set_global_assignment -name VERILOG_FILE ../../../src/cam.v
-set_global_assignment -name VERILOG_FILE ../../../src/controller.v
-set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v
-set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v
-set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v
-set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v
-set_global_assignment -name VERILOG_FILE ../../../src/fcs.v
-set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v
-set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v
-set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v
-set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v
-set_global_assignment -name VERILOG_FILE ../../../src/mdio.v
-set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v
-set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v
-set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v
-set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v
-set_global_assignment -name VERILOG_FILE ../../../src/rm.v
-set_global_assignment -name VERILOG_FILE ../../../src/switch.v
-set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v
-set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v
-set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v
-set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip
-set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip
-set_global_assignment -name QIP_FILE ip/pll/pll.qip
-set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip
-set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id tst_controller
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id tst_controller
@@ -738,5 +706,38 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id tst_controller
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id tst_controller
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id tst_controller
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/sim/win" -section_id eda_simulation
+set_global_assignment -name SDC_FILE betsy.sdc
+set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp
+set_global_assignment -name VERILOG_FILE src/betsy.v
+set_global_assignment -name VERILOG_FILE ../../../src/cam.v
+set_global_assignment -name VERILOG_FILE ../../../src/controller.v
+set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v
+set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v
+set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v
+set_global_assignment -name VERILOG_FILE ../../../src/fcs.v
+set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v
+set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v
+set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v
+set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v
+set_global_assignment -name VERILOG_FILE ../../../src/mdio.v
+set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v
+set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v
+set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v
+set_global_assignment -name VERILOG_FILE ../../../src/pkt_gen.v
+set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v
+set_global_assignment -name VERILOG_FILE ../../../src/switch.v
+set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v
+set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v
+set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v
+set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip
+set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip
+set_global_assignment -name QIP_FILE ip/pll/pll.qip
+set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip
+set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/betsy_auto_stripped.stp \ No newline at end of file
diff --git a/manufacturer/altera/cyclone10_lp/src/betsy.v b/manufacturer/altera/cyclone10_lp/src/betsy.v
index ccefd3b..75d419a 100644
--- a/manufacturer/altera/cyclone10_lp/src/betsy.v
+++ b/manufacturer/altera/cyclone10_lp/src/betsy.v
@@ -248,7 +248,7 @@ module betsy (
wire [NUM_PHYS-1:0] mode_100Mbit;
// Controller Peripheral Address Decode and Select
- wire mac_sel, pkt_filter_sel, mle_sel;
+ wire mac_sel, pkt_filter_sel, mle_sel, pkt_gen_sel;
wire [1:0] mac_addr;
wire [15:0] pkt_filter_addr;
@@ -291,8 +291,9 @@ module betsy (
wire [31:0] mem_d_o;
wire mem_we, mem_oe;
wire mem_tgt_ready, mem_tgt_ready_mac_0, mem_tgt_ready_mac_1;
+ wire mem_tgt_ready_mle, mem_tgt_ready_pkt_gen;
wire [15:0] mac_0_d_o, mac_1_d_o, mac_2_d_o;
- wire [15:0] mle_d_o;
+ wire [15:0] mle_d_o, pkt_gen_d_o;
wire [10:0] hfifo_d_o;
// half FIFO / Interface for Controller
@@ -523,6 +524,7 @@ module betsy (
.pkt_filter_sel(pkt_filter_sel),
.mac_sel(mac_sel),
.mle_sel(mle_sel),
+ .pkt_gen_sel(pkt_gen_sel),
.hf_ptrs_sel(hf_ptrs_sel),
.hf_rx_sel(hf_rx_sel),
.hf_tx_sel(hf_tx_sel),
@@ -551,18 +553,19 @@ module betsy (
);
- assign mem_tgt_ready = mem_tgt_ready_mac_0 && mem_tgt_ready_mac_1;
+ assign mem_tgt_ready = mem_tgt_ready_mac_0 | mem_tgt_ready_mac_1 | mem_tgt_ready_mle | mem_tgt_ready_pkt_gen;
// controller data mux
always @(*)
- casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, mle_sel, mac_sel, mac_addr})
- 7'b0000100: mem_d_i = {16'h0000, mac_0_d_o};
- 7'b0000101: mem_d_i = {16'h0000, mac_1_d_o};
- 7'b0000110: mem_d_i = {16'h0000, mac_2_d_o};
- 7'b00010??: mem_d_i = {16'h0000, mle_d_o};
- 7'b00100??: mem_d_i = {21'h0000, hfifo_d_o};
- 7'b01000??: mem_d_i = {21'h0000, hfifo_d_o};
- 7'b10000??: mem_d_i = {21'h0000, hfifo_d_o};
+ casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, pkt_gen_sel, mle_sel, mac_sel, mac_addr})
+ 8'b00000100: mem_d_i = {16'h0000, mac_0_d_o};
+ 8'b00000101: mem_d_i = {16'h0000, mac_1_d_o};
+ 8'b00000110: mem_d_i = {16'h0000, mac_2_d_o};
+ 8'b000010??: mem_d_i = {16'h0000, mle_d_o};
+ 8'b000100??: mem_d_i = {16'h0000, pkt_gen_d_o};
+ 8'b001000??: mem_d_i = {21'h0000, hfifo_d_o};
+ 8'b010000??: mem_d_i = {21'h0000, hfifo_d_o};
+ 8'b100000??: mem_d_i = {21'h0000, hfifo_d_o};
default: mem_d_i = 32'd0;
endcase
@@ -695,6 +698,24 @@ module betsy (
.fifo_d_o(mle_fifo_d_o),
.byte_cnt(rx_mle_byte_cnt)
);
+
+ pkt_gen pkt_gen_0(
+ .rstn(sys_rstn),
+ .pclk(pclk),
+ // controller interface
+ .cont_clk(cont_clk),
+ .cont_sel(pkt_gen_sel),
+ .cont_we(mem_we),
+ .cont_addr(mem_addr),
+ .cont_d_i(mem_d_o[15:0]),
+ .cont_d_o(pkt_gen_d_o),
+ .cont_tgt_ready(mem_tgt_ready_pkt_gen),
+ // switch interface
+ .fifo_empty_o(),
+ .fifo_re(1'b0),
+ .fifo_d_o(),
+ .byte_cnt()
+ );
/*
* Controls the routing of data and transmit modes
diff --git a/src/cont_params.v b/src/cont_params.v
index c9f85c2..d871534 100644
--- a/src/cont_params.v
+++ b/src/cont_params.v
@@ -40,15 +40,14 @@ localparam MSG_TYPE_REPLY_SUCCESS = 8'h3;
localparam MSG_TYPE_REPLY_ERROR = 8'h4;
localparam MSG_TYPE_NOTIY = 8'h5;
-
localparam MSG_CONTROLLER_ADDR = 16'h0000;
localparam MSG_MAC_ADDR = 16'h0100;
localparam MSG_PKT_FILTER_ADDR = 16'h0200;
localparam MSG_SWITCH_ADDR = 16'h0500;
localparam MSG_MDIO_ADDR = 16'h0600;
localparam MSG_MLE_ADDR = 16'h0700;
-localparam MSG_INVALID_ADDR = 16'h0800;
-
+localparam MSG_PKT_GEN_ADDR = 16'h0800;
+localparam MSG_INVALID_ADDR = 16'h0900;
localparam HF_TX_WR_PTR_ADDR = 16'd0;
localparam HF_TX_RD_PTR_ADDR = 16'd1; // read only
diff --git a/src/controller.v b/src/controller.v
index e30d461..922a9f0 100644
--- a/src/controller.v
+++ b/src/controller.v
@@ -48,6 +48,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
output reg pkt_filter_sel,
output reg mac_sel,
output reg mle_sel,
+ output reg pkt_gen_sel,
output reg hf_ptrs_sel,
output reg hf_tx_sel,
output reg hf_rx_sel,
@@ -341,6 +342,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
{MSG_MAC_ADDR[15:8],8'h??}: msg_response <= mem_d_i;
{MSG_MDIO_ADDR[15:8],8'h??}: msg_response <= mdio_d;
{MSG_MLE_ADDR[15:8],8'h??}: msg_response <= mem_d_i;
+ {MSG_PKT_GEN_ADDR[15:8],8'h??}: msg_response <= mem_d_i;
default: msg_response <= mem_d_i[15:0];
endcase
@@ -486,7 +488,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
mem_cmd <= 1'b0;
else if (cont_state == CONT_ST_IDLE && !rx_msg_captured)
mem_cmd <= 1'b0;
- else if (rx_msg_captured && msg_addr[15:8] >= MSG_MAC_ADDR[15:8] && msg_addr[15:8] < MSG_MLE_ADDR[15:8])
+ else if (rx_msg_captured && msg_addr[15:8] >= MSG_MAC_ADDR[15:8] && msg_addr[15:8] < MSG_INVALID_ADDR[15:8])
mem_cmd <= 1'b1;
// Primary Memory Controller Actions
@@ -498,6 +500,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
mac_sel <= 1'b0;
mle_sel <= 1'b0;
pkt_filter_sel <= 1'b0;
+ pkt_gen_sel <= 1'b0;
hf_ptrs_sel <= 1'b0;
hf_tx_sel <= 1'b0;
hf_rx_sel <= 1'b0;
@@ -534,6 +537,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
MSG_MAC_ADDR[15:8]: mac_sel <= 1'b1;
MSG_PKT_FILTER_ADDR[15:8]: pkt_filter_sel <= 1'b1;
MSG_MLE_ADDR[15:8]: mle_sel <= 1'b1;
+ MSG_PKT_GEN_ADDR[15:8]: pkt_gen_sel <= 1'b1;
endcase
end
end
@@ -544,6 +548,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
mac_sel <= 1'b0;
mle_sel <= 1'b0;
pkt_filter_sel <= 1'b0;
+ pkt_gen_sel <= 1'b0;
end
else if (mem_state == MEM_ST_REPLY_START && tx_fifo_empty) begin // write byte cnt
hf_ptrs_sel <= 1'b1;
@@ -606,6 +611,7 @@ module controller #(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
hf_ptrs_sel <= 1'b0;
hf_tx_sel <= 1'b0;
hf_rx_sel <= 1'b0;
+ pkt_gen_sel <= 1'b0;
end
// rx_cnt
diff --git a/src/pkt_gen.v b/src/pkt_gen.v
new file mode 100644
index 0000000..819322d
--- /dev/null
+++ b/src/pkt_gen.v
@@ -0,0 +1,80 @@
+/*
+ * pkt_gen.v
+ *
+ * Copyright (C) 2026 Private Island Networks Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * function: programmable packet generator
+ *
+ * see https://privateisland.tech/dev/pi-pkt-gen
+ *
+ */
+
+module pkt_gen #(parameter DEPTH = 8, parameter DATAW = 16)
+(
+ input rstn,
+ input pclk,
+
+ // controller interface
+ input cont_clk,
+ input cont_sel,
+ input cont_we,
+ input [$clog2(DEPTH)-1:0] cont_addr,
+ input [DATAW-1:0] cont_d_i,
+ output reg [DATAW-1:0] cont_d_o,
+ output cont_tgt_ready,
+
+ // switch interface
+ output fifo_empty_o,
+ input fifo_re,
+ output [8:0] fifo_d_o,
+ output [10:0] byte_cnt
+);
+
+ /*** local params ***/
+
+ localparam PKT_GEN_ENABLE_ADDR = 'h0;
+
+ /*** variables ***/
+ reg pkt_gen_en;
+
+ /*** logic ***/
+
+ // mle_enable: enable / disable the MLE
+ always @(posedge cont_clk, negedge rstn)
+ if (!rstn)
+ pkt_gen_en <= 1'b0;
+ else if (cont_we && cont_sel && cont_addr == PKT_GEN_ENABLE_ADDR)
+ pkt_gen_en <= cont_d_i[0];
+
+ // Controller Read Data Mux
+ always @(posedge cont_clk, negedge rstn)
+ if (!rstn)
+ cont_d_o <= 16'hcccc;
+ else
+ case (cont_addr)
+ PKT_GEN_ENABLE_ADDR: cont_d_o <= pkt_gen_en;
+ default: cont_d_o <= cont_d_o;
+ endcase
+
+ // tie offs for now
+ assign cont_tgt_ready = 1'b1;
+ assign fifo_empty_o = 1'b0;
+ assign fifo_d_o = 9'h1ff;
+ assign byte_cnt = 'd0;
+
+
+
+endmodule
+
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-07-03 18:15:24 +0000

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