pkt_gen: create first pass skelton source file and changes to support packet generation

1 files changed, 80 insertions, 0 deletions

diff --git a/src/pkt_gen.v b/src/pkt_gen.v
new file mode 100644
index 0000000..819322d
--- /dev/null
+++ b/src/pkt_gen.v
@@ -0,0 +1,80 @@
+/* 
+ *	 pkt_gen.v
+ *
+ *	 Copyright (C) 2026 Private Island Networks Inc.
+ *
+ *   Licensed under the Apache License, Version 2.0 (the "License");
+ *   you may not use this file except in compliance with the License.
+ *   You may obtain a copy of the License at
+ *
+ *       http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *   Unless required by applicable law or agreed to in writing, software
+ *   distributed under the License is distributed on an "AS IS" BASIS,
+ *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *   See the License for the specific language governing permissions and
+ *   limitations under the License.
+ *
+ *	function: programmable packet generator
+ *
+ *	see https://privateisland.tech/dev/pi-pkt-gen
+ *	 
+ */
+ 
+module pkt_gen #(parameter DEPTH = 8, parameter DATAW = 16)
+(
+	input	rstn,
+	input	pclk,
+	
+	// controller interface
+	input  	cont_clk,
+	input   cont_sel,
+	input 	cont_we,
+	input 	[$clog2(DEPTH)-1:0] cont_addr,
+	input 	[DATAW-1:0]	cont_d_i,
+	output reg [DATAW-1:0] cont_d_o,
+	output cont_tgt_ready,
+	
+	// switch interface
+	output fifo_empty_o,
+	input fifo_re,
+	output [8:0] fifo_d_o,
+	output [10:0] byte_cnt
+);
+
+	/*** local params ***/
+	
+	localparam PKT_GEN_ENABLE_ADDR = 'h0;
+
+	/*** variables ***/
+	reg pkt_gen_en;
+
+	/*** logic ***/
+
+	// mle_enable: enable / disable the MLE
+	always @(posedge cont_clk, negedge rstn)
+		if (!rstn)
+			pkt_gen_en <= 1'b0;
+		else if (cont_we && cont_sel && cont_addr == PKT_GEN_ENABLE_ADDR)
+			pkt_gen_en <= cont_d_i[0];
+			
+	// Controller Read Data Mux
+	always @(posedge cont_clk, negedge rstn)
+		if (!rstn)
+			cont_d_o <= 16'hcccc;
+		else
+			case (cont_addr)
+				PKT_GEN_ENABLE_ADDR: cont_d_o <=  pkt_gen_en;
+				default: cont_d_o <= cont_d_o;
+			endcase	
+			
+	// tie offs for now
+	assign cont_tgt_ready = 1'b1;
+	assign fifo_empty_o = 1'b0;
+	assign fifo_d_o = 9'h1ff;
+	assign byte_cnt = 'd0;
+	
+	
+		
+endmodule
+