diff options
| author | Private Island Networks Inc <opensource@privateisland.tech> | 2026-06-30 14:34:45 -0400 |
|---|---|---|
| committer | Private Island Networks Inc <opensource@privateisland.tech> | 2026-06-30 14:34:45 -0400 |
| commit | 7d8b0ec0dd703db060c527537bd9da7798cf86e6 (patch) | |
| tree | 7476a02a9410dd884c3a763da2d8268f3ea84180 /manufacturer/altera/cyclone10_lp/src | |
| parent | 2d95906292d0cc91f3ec8aa20298c646b934a7ab (diff) | |
pkt_gen: create first pass skelton source file and changes to support packet generation
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/src')
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/src/betsy.v | 43 |
1 files changed, 32 insertions, 11 deletions
diff --git a/manufacturer/altera/cyclone10_lp/src/betsy.v b/manufacturer/altera/cyclone10_lp/src/betsy.v index ccefd3b..75d419a 100644 --- a/manufacturer/altera/cyclone10_lp/src/betsy.v +++ b/manufacturer/altera/cyclone10_lp/src/betsy.v @@ -248,7 +248,7 @@ module betsy ( wire [NUM_PHYS-1:0] mode_100Mbit; // Controller Peripheral Address Decode and Select - wire mac_sel, pkt_filter_sel, mle_sel; + wire mac_sel, pkt_filter_sel, mle_sel, pkt_gen_sel; wire [1:0] mac_addr; wire [15:0] pkt_filter_addr; @@ -291,8 +291,9 @@ module betsy ( wire [31:0] mem_d_o; wire mem_we, mem_oe; wire mem_tgt_ready, mem_tgt_ready_mac_0, mem_tgt_ready_mac_1; + wire mem_tgt_ready_mle, mem_tgt_ready_pkt_gen; wire [15:0] mac_0_d_o, mac_1_d_o, mac_2_d_o; - wire [15:0] mle_d_o; + wire [15:0] mle_d_o, pkt_gen_d_o; wire [10:0] hfifo_d_o; // half FIFO / Interface for Controller @@ -523,6 +524,7 @@ module betsy ( .pkt_filter_sel(pkt_filter_sel), .mac_sel(mac_sel), .mle_sel(mle_sel), + .pkt_gen_sel(pkt_gen_sel), .hf_ptrs_sel(hf_ptrs_sel), .hf_rx_sel(hf_rx_sel), .hf_tx_sel(hf_tx_sel), @@ -551,18 +553,19 @@ module betsy ( ); - assign mem_tgt_ready = mem_tgt_ready_mac_0 && mem_tgt_ready_mac_1; + assign mem_tgt_ready = mem_tgt_ready_mac_0 | mem_tgt_ready_mac_1 | mem_tgt_ready_mle | mem_tgt_ready_pkt_gen; // controller data mux always @(*) - casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, mle_sel, mac_sel, mac_addr}) - 7'b0000100: mem_d_i = {16'h0000, mac_0_d_o}; - 7'b0000101: mem_d_i = {16'h0000, mac_1_d_o}; - 7'b0000110: mem_d_i = {16'h0000, mac_2_d_o}; - 7'b00010??: mem_d_i = {16'h0000, mle_d_o}; - 7'b00100??: mem_d_i = {21'h0000, hfifo_d_o}; - 7'b01000??: mem_d_i = {21'h0000, hfifo_d_o}; - 7'b10000??: mem_d_i = {21'h0000, hfifo_d_o}; + casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, pkt_gen_sel, mle_sel, mac_sel, mac_addr}) + 8'b00000100: mem_d_i = {16'h0000, mac_0_d_o}; + 8'b00000101: mem_d_i = {16'h0000, mac_1_d_o}; + 8'b00000110: mem_d_i = {16'h0000, mac_2_d_o}; + 8'b000010??: mem_d_i = {16'h0000, mle_d_o}; + 8'b000100??: mem_d_i = {16'h0000, pkt_gen_d_o}; + 8'b001000??: mem_d_i = {21'h0000, hfifo_d_o}; + 8'b010000??: mem_d_i = {21'h0000, hfifo_d_o}; + 8'b100000??: mem_d_i = {21'h0000, hfifo_d_o}; default: mem_d_i = 32'd0; endcase @@ -695,6 +698,24 @@ module betsy ( .fifo_d_o(mle_fifo_d_o), .byte_cnt(rx_mle_byte_cnt) ); + + pkt_gen pkt_gen_0( + .rstn(sys_rstn), + .pclk(pclk), + // controller interface + .cont_clk(cont_clk), + .cont_sel(pkt_gen_sel), + .cont_we(mem_we), + .cont_addr(mem_addr), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(pkt_gen_d_o), + .cont_tgt_ready(mem_tgt_ready_pkt_gen), + // switch interface + .fifo_empty_o(), + .fifo_re(1'b0), + .fifo_d_o(), + .byte_cnt() + ); /* * Controls the routing of data and transmit modes |
