gpio: first pass changes to support new GPIO daughter boardgpio

1 files changed, 69 insertions, 12 deletions

diff --git a/manufacturer/altera/cyclone10_lp/src/betsy.v b/manufacturer/altera/cyclone10_lp/src/betsy.v
index ccefd3b..c388429 100644
--- a/manufacturer/altera/cyclone10_lp/src/betsy.v
+++ b/manufacturer/altera/cyclone10_lp/src/betsy.v
@@ -21,8 +21,9 @@
  */ 
 
 // `define PASSTHROUGH
-`define PHY2_PRESENT
-
+//`define PHY2_PRESENT
+`define GPIO_PRESENT
+ 
 module  betsy (
 	input rstn,
 	input clk_i,			// 25Mhz
@@ -70,6 +71,13 @@ module  betsy (
 	input phy1_intn,
 	inout [1:0] phy1_gpio,
 	
+//====================================	
+// Replaced PHY2 to GPIO if deteced.
+// If not replaced, PHY2 continues.	
+//====================================
+`ifdef GPIO_PRESENT
+	inout [19:0] gpio,
+`else
 	// PHY2 RGMII
 	output phy2_rstn,
 	
@@ -86,6 +94,7 @@ module  betsy (
 	
 	input phy2_intn,
 	inout [1:0] phy2_gpio,
+`endif
 	
 	// FLASH
 	output flash_clk,
@@ -111,6 +120,18 @@ module  betsy (
 	reg sys_rstn;
 	wire cont_clk, clk_25, clk_125;
 	wire pclk;				// main fabric clock for Ethernet pipeline
+	
+// ============================================================
+// GPIO INTERNAL SIGNALS
+// These wires separate input, output, and direction control
+// for the bidirectional GPIO pins.
+// ============================================================
+`ifdef GPIO_PRESENT
+   wire [19:0] gpio_in;
+   wire [19:0] gpio_out;
+   wire [19:0] gpio_out_en;
+`endif
+
 	reg [3:0] cnt_init;
 	reg [25:0]  heart_beat_cnt;
 	wire [NUM_PHYS-1:0] phy_up;
@@ -345,6 +366,23 @@ module  betsy (
 	assign phy1_clk = clk_25;
 	assign pclk = clk_125;
 	
+// ============================================================
+// GPIO CONTROL
+// Implements bidirectional behavior for GPIO pins.
+// If gpio_out_en[i] = 1 → pin drives gpio_out[i]
+// If gpio_out_en[i] = 0 → pin is high impedance (input mode)
+// ============================================================
+`ifdef GPIO_PRESENT
+    genvar i;
+    generate
+        for (i = 0; i < 20; i = i + 1) begin : gpio_tri
+            assign gpio[i] = gpio_out_en[i] ? gpio_out[i] : 1'bz;
+        end
+    endgenerate
+
+    assign gpio_in = gpio;
+`endif
+	
 	always @(posedge cont_clk, negedge rstn)
 		if (!rstn)
 			cnt_init <= 4'd0;
@@ -362,12 +400,19 @@ module  betsy (
 	// TODO: Review sequence and move to Controller control
 	assign phy0_rstn = sys_rstn;
 	assign phy1_rstn = pll_locked;
+
+`ifndef GPIO_PRESENT
 	assign phy2_rstn = pll_locked;
+`endif
 	
 	// TODO: Fix this
 	assign phy_resetn = {pll_locked, pll_locked, pll_locked};
 	
-	assign phy_int = {~phy2_intn, ~phy1_intn, ~phy0_intn};
+`ifdef GPIO_PRESENT
+    assign phy_int = {1'b0, ~phy1_intn, ~phy0_intn};   // PHY2 slot tied off
+`else
+    assign phy_int = {~phy2_intn, ~phy1_intn, ~phy0_intn};
+`endif
 		
 	// TODO: This will be replaced when the SPI master peripheral is ready
 	assign flash_d = 8'hab;
@@ -379,10 +424,14 @@ module  betsy (
 	// TODO: Gate these when not in use
 	assign phy0_mdc = cont_clk;
 	assign phy1_mdc = cont_clk;
-	assign phy2_mdc = cont_clk;
+`ifndef GPIO_PRESENT
+assign phy2_mdc = cont_clk;
+`endif
 	
-	assign phy2_gpio[0] = gpio_ipv4[0];
-	assign phy2_gpio[1] = gpio_ipv4[1];
+`ifndef GPIO_PRESENT
+    assign phy2_gpio[0] = gpio_ipv4[0];
+    assign phy2_gpio[1] = gpio_ipv4[1];
+`endif
 	
 	
 	// Bits 3:0 on the positive edge of RX_CLK and bits 7:4 on the negative edge of RX_CLK.
@@ -400,12 +449,14 @@ module  betsy (
 			.dataout_l ({rx1_ctl_i[1],rx1_d_i[7:4]})
 		);
 		
-	ddri	rgmi_rx_2 (
-			.datain ({phy2_rx_ctl, phy2_rx_d}),
-			.inclock (phy2_rx_clk),
-			.dataout_h ({rx2_ctl_i[0],rx2_d_i[3:0]}),
-			.dataout_l ({rx2_ctl_i[1],rx2_d_i[7:4]})
+`ifndef GPIO_PRESENT
+	ddri rgmi_rx_2 (
+		.datain ({phy2_rx_ctl, phy2_rx_d}),
+		.inclock (phy2_rx_clk),
+		.dataout_h ({rx2_ctl_i[0],rx2_d_i[3:0]}),
+		.dataout_l ({rx2_ctl_i[1],rx2_d_i[7:4]})
 		);
+`endif
 
 
 	// Simple Pipeline to Make Timing
@@ -547,7 +598,13 @@ module  betsy (
 		.phy_resetn(),
 		.mac_reset(mac_reset),
 		// Debug
+	`ifdef GPIO_PRESENT
+		.gpio_in(gpio_in),
+		.gpio_out(gpio_out),
+		.gpio_out_en(gpio_out_en)
+	`else
 		.gpio(gpio_controller)
+	`endif
 	
 	);
 	
@@ -1911,4 +1968,4 @@ module  betsy (
 	assign fpga_led[1] = heart_beat_cnt[23];
 	assign fpga_led[2] = evt_toggle;
 
-endmodule
+endmodule
\ No newline at end of file