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/*
* flexbus.h
*
* Copyright (C) 2018, 2019 Mind Chasers Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef FLEXBUS_H_
#define FLEXBUS_H_
// CREGS Bit Definitions
#define MEM_SEL_DCU 0x0
#define MEM_SEL_DPR 0x1
#define RESET_HFIFO_PTRS 0x4
// Flex Bus Memory Map
#define MRAM_START_ADDRESS 0x60000000U
#define CREG_MEM_SEL MRAM_START_ADDRESS
#define CREG_IACK MRAM_START_ADDRESS+1
// Flex Bus Base Offsets for DCU
#define DCU_SCI_CH0 MRAM_START_ADDRESS+0x000
#define DCU_SCI_CH1 MRAM_START_ADDRESS+0x040
#define DCU_DUAL1 MRAM_START_ADDRESS+0x080
#define DCU_SCI_CH2 MRAM_START_ADDRESS+0x100
#define DCU_SCI_SPARE MRAM_START_ADDRESS+0x140
#define DCU_DUAL0 MRAM_START_ADDRESS+0x180
// Flex Bus Base Offsets for DPRAM
#define DPRAM_RX MRAM_START_ADDRESS+0x000
#define DPRAM_TX MRAM_START_ADDRESS+0x040
#define DPRAM_META MRAM_START_ADDRESS+0x080
#endif /* FLEXBUS_H_ */
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