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10 daysinitial v02 commit with inclusion of ftdi and power snippetsPrivate Island Networks Inc.
2026-06-23start cleaning up split power plane, remove mounting holes from RJ45 symbolPrivate Island Networks Inc.
2026-06-22add globals for FLASH nets, so they connect between sheetsPrivate Island Networks Inc.
2026-06-21initial commit after restarting project using schematic imports and manual ↵mainPrivate Island Networks Inc.
symbol cleanup
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-07-24 04:46:42 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis