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3 dayssymbols: clean up schematic symbol file and add three missing footprintsPrivate Island Networks Inc
9 dayspcb: remove HLE alignment pins, realign layers, move power snippet into placePrivate Island Networks Inc.
2026-07-06FOOTPRINTS: clean up several footprints to be consistent with Kicad layers ↵Private Island Networks Inc.
and resolve some DRCs
2026-06-22add globals for FLASH nets, so they connect between sheetsPrivate Island Networks Inc.
2026-06-21initial commit after restarting project using schematic imports and manual ↵mainPrivate Island Networks Inc.
symbol cleanup
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-07-24 04:45:34 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis