index
:
betsy
main
v01
v02
Betsy Maker Board,Open Source KiCad Project
Private Island Networks Inc.
summary
refs
log
tree
commit
diff
homepage
log msg
author
committer
range
Age
Commit message (
Collapse
)
Author
10 days
reset and re-annotate all reference designators to use X 100 convention
Private Island Networks Inc.
11 days
initial v02 commit with inclusion of ftdi and power snippets
Private Island Networks Inc.
2026-07-08
pcb: further clean up and order some test boards
HEAD
v01
Private Island Networks Inc.
2026-07-06
design files: DRC clean up of 400+ errors and warnings. Remaining errors ↵
Private Island Networks Inc.
and warnings may be OK or Kicad bugs
2026-07-06
jobset: configure GERBER and DRILL file settings as needed for PCB fabrication
Private Island Networks Inc.
2026-07-06
FOOTPRINTS: clean up several footprints to be consistent with Kicad layers ↵
Private Island Networks Inc.
and resolve some DRCs
2026-06-23
add CERN license and update files to reference it
Private Island Networks Inc.
2026-06-23
start cleaning up split power plane, remove mounting holes from RJ45 symbol
Private Island Networks Inc.
2026-06-22
add globals for FLASH nets, so they connect between sheets
Private Island Networks Inc.
2026-06-22
finish manual anotation of reference designators to align with Altium Betsy
Private Island Networks Inc.
2026-06-21
labels: Start using global labels and combining pages
Private Island Networks Inc.
2026-06-21
initial commit after restarting project using schematic imports and manual ↵
main
Private Island Networks Inc.
symbol cleanup
Highly Recommended Verilog Books