finish manual anotation of reference designators to align with Altium Betsy

1 files changed, 5944 insertions, 5950 deletions

diff --git a/Betsy.kicad_pcb b/Betsy.kicad_pcb
index 2784411..eea7392 100644
--- a/Betsy.kicad_pcb
+++ b/Betsy.kicad_pcb
@@ -590,7 +590,7 @@
 			(at 0.75 0 90)
 			(size 0.8 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_LED0")
+			(net "/RGMII1/PHY1_LED0")
 			(pinfunction "A_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02053)
@@ -1878,7 +1878,7 @@
 			(at 0.75 0 90)
 			(size 0.8 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_LED0")
+			(net "/RGMII0/PHY0_LED0")
 			(pinfunction "A_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02053)
@@ -5537,7 +5537,7 @@
 			(at 1.2 -6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_TX_D3")
+			(net "/Expansion/PHY2_RGMII_TX_D3")
 			(pinfunction "IO,_DIFFIO_T16N_A10")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5548,7 +5548,7 @@
 			(at 2 -6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_TX_D2")
+			(net "/Expansion/PHY2_RGMII_TX_D2")
 			(pinfunction "IO,_DIFFIO_T20N_A11")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5559,7 +5559,7 @@
 			(at 2.8 -6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_TX_D0")
+			(net "/Expansion/PHY2_RGMII_TX_D0")
 			(pinfunction "IO,_DIFFIO_T21N_A12")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5570,7 +5570,7 @@
 			(at 3.6 -6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_TX_D1")
+			(net "/Expansion/PHY2_RGMII_TX_D1")
 			(pinfunction "IO,_DIFFIO_T22N_A13")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5581,7 +5581,7 @@
 			(at 4.4 -6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_TX_CTL")
+			(net "/Expansion/PHY2_RGMII_TX_CTL")
 			(pinfunction "IO,_PLL2_CLKOUTN_A14")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5592,7 +5592,7 @@
 			(at 5.2 -6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_TX_CLK")
+			(net "/Expansion/PHY2_RGMII_TX_CLK")
 			(pinfunction "IO_B7_0_A15")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5757,7 +5757,7 @@
 			(at 4.4 -5.2)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RESET#")
+			(net "/Expansion/PHY2_RESET#")
 			(pinfunction "IO,_PLL2_CLKOUTP_B14")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5779,7 +5779,7 @@
 			(at 6 -5.2)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_GPIO1")
+			(net "/Expansion/PHY2_GPIO1")
 			(pinfunction "IO_B6_1_B16")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -5955,7 +5955,7 @@
 			(at 6 -4.4)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_GPIO0")
+			(net "/Expansion/PHY2_GPIO0")
 			(pinfunction "IO,_DIFFIO_R1N_C16")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6120,7 +6120,7 @@
 			(at 5.2 -3.6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_INTN")
+			(net "/Expansion/PHY2_INTN")
 			(pinfunction "IO_B6_3_D15")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6131,7 +6131,7 @@
 			(at 6 -3.6)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_RX_D0")
+			(net "/Expansion/PHY2_RGMII_RX_D0")
 			(pinfunction "IO_B6_2_D16")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6307,7 +6307,7 @@
 			(at 6 -2.8)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_RX_CLK")
+			(net "/Expansion/PHY2_RGMII_RX_CLK")
 			(pinfunction "CLK5,_DIFFCLK_2N_E16")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6472,7 +6472,7 @@
 			(at 5.2 -2)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_RX_D1")
+			(net "/Expansion/PHY2_RGMII_RX_D1")
 			(pinfunction "IO,_DIFFIO_R4P,_CLKUSR_F15")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6483,7 +6483,7 @@
 			(at 6 -2)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_RX_CTL")
+			(net "/Expansion/PHY2_RGMII_RX_CTL")
 			(pinfunction "IO,_DIFFIO_R4N,_NCEO_F16")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6648,7 +6648,7 @@
 			(at 5.2 -1.2)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_RX_D3")
+			(net "/Expansion/PHY2_RGMII_RX_D3")
 			(pinfunction "IO,_DIFFIO_R5P,_CRC_ERROR_G15")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6659,7 +6659,7 @@
 			(at 6 -1.2)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/PHY2_RGMII_RX_D2")
+			(net "/Expansion/PHY2_RGMII_RX_D2")
 			(pinfunction "IO,_DIFFIO_R5N,_INIT_DONE_G16")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -6813,7 +6813,7 @@
 			(at 4.4 -0.4)
 			(size 0.4 0.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/RGMII2/CONF_DONE")
+			(net "/Expansion/CONF_DONE")
 			(pinfunction "CONF_DONE_H14")
 			(pintype "passive")
 			(solder_paste_margin -0.2)
@@ -10456,7 +10456,7 @@
 			(at -5.4483 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_D_P")
+			(net "/RGMII0/PHY0_TD_D_P")
 			(pinfunction "TD1+_1")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10466,7 +10466,7 @@
 			(at -4.4577 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_D_N")
+			(net "/RGMII0/PHY0_TD_D_N")
 			(pinfunction "TD1-_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10496,7 +10496,7 @@
 			(at -1.4859 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_C_P")
+			(net "/RGMII0/PHY0_TD_C_P")
 			(pinfunction "TD2+_5")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10506,7 +10506,7 @@
 			(at -0.4953 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_C_N")
+			(net "/RGMII0/PHY0_TD_C_N")
 			(pinfunction "TD2-_6")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10516,7 +10516,7 @@
 			(at 0.4953 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_B_P")
+			(net "/RGMII0/PHY0_TD_B_P")
 			(pinfunction "TD3+_7")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10526,7 +10526,7 @@
 			(at 1.4859 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_B_N")
+			(net "/RGMII0/PHY0_TD_B_N")
 			(pinfunction "TD3-_8")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10556,7 +10556,7 @@
 			(at 4.4577 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_A_P")
+			(net "/RGMII0/PHY0_TD_A_P")
 			(pinfunction "TD4+_11")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10566,7 +10566,7 @@
 			(at 5.4483 4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_A_N")
+			(net "/RGMII0/PHY0_TD_A_N")
 			(pinfunction "TD4-_12")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10576,7 +10576,7 @@
 			(at 5.4483 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DA_N")
+			(net "/RGMII0/PHY0_DA_N")
 			(pinfunction "MX4-_13")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10586,7 +10586,7 @@
 			(at 4.4577 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DA_P")
+			(net "/RGMII0/PHY0_DA_P")
 			(pinfunction "MX4+_14")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10616,7 +10616,7 @@
 			(at 1.4859 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DB_N")
+			(net "/RGMII0/PHY0_DB_N")
 			(pinfunction "MX3-_17")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10626,7 +10626,7 @@
 			(at 0.4953 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DB_P")
+			(net "/RGMII0/PHY0_DB_P")
 			(pinfunction "MX3+_18")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10636,7 +10636,7 @@
 			(at -0.4953 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DC_N")
+			(net "/RGMII0/PHY0_DC_N")
 			(pinfunction "MX2-_19")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10646,7 +10646,7 @@
 			(at -1.4859 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DC_P")
+			(net "/RGMII0/PHY0_DC_P")
 			(pinfunction "MX2+_20")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10676,7 +10676,7 @@
 			(at -4.4577 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DD_N")
+			(net "/RGMII0/PHY0_DD_N")
 			(pinfunction "MX1-_23")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -10686,7 +10686,7 @@
 			(at -5.4483 -4.699 90)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_DD_P")
+			(net "/RGMII0/PHY0_DD_P")
 			(pinfunction "MX1+_24")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -11960,7 +11960,7 @@
 			(size 0.6 0.55)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.075)
-			(net "/PHY0 TI/PHY0_RBIAS")
+			(net "/RGMII0/PHY0_RBIAS")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -13820,7 +13820,7 @@
 			(at 0.75 0 90)
 			(size 0.8 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_LED2")
+			(net "/RGMII1/PHY1_LED2")
 			(pinfunction "A_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02053)
@@ -14631,7 +14631,7 @@
 			(at -5.4483 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_D_P")
+			(net "/RGMII1/PHY1_TD_D_P")
 			(pinfunction "TD1+_1")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14641,7 +14641,7 @@
 			(at -4.4577 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_D_N")
+			(net "/RGMII1/PHY1_TD_D_N")
 			(pinfunction "TD1-_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14671,7 +14671,7 @@
 			(at -1.4859 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_C_P")
+			(net "/RGMII1/PHY1_TD_C_P")
 			(pinfunction "TD2+_5")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14681,7 +14681,7 @@
 			(at -0.4953 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_C_N")
+			(net "/RGMII1/PHY1_TD_C_N")
 			(pinfunction "TD2-_6")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14691,7 +14691,7 @@
 			(at 0.4953 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_B_P")
+			(net "/RGMII1/PHY1_TD_B_P")
 			(pinfunction "TD3+_7")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14701,7 +14701,7 @@
 			(at 1.4859 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_B_N")
+			(net "/RGMII1/PHY1_TD_B_N")
 			(pinfunction "TD3-_8")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14731,7 +14731,7 @@
 			(at 4.4577 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_A_P")
+			(net "/RGMII1/PHY1_TD_A_P")
 			(pinfunction "TD4+_11")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14741,7 +14741,7 @@
 			(at 5.4483 4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_TD_A_N")
+			(net "/RGMII1/PHY1_TD_A_N")
 			(pinfunction "TD4-_12")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14751,7 +14751,7 @@
 			(at 5.4483 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DA_N")
+			(net "/RGMII1/PHY1_DA_N")
 			(pinfunction "MX4-_13")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14761,7 +14761,7 @@
 			(at 4.4577 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DA_P")
+			(net "/RGMII1/PHY1_DA_P")
 			(pinfunction "MX4+_14")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14791,7 +14791,7 @@
 			(at 1.4859 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DB_N")
+			(net "/RGMII1/PHY1_DB_N")
 			(pinfunction "MX3-_17")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14801,7 +14801,7 @@
 			(at 0.4953 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DB_P")
+			(net "/RGMII1/PHY1_DB_P")
 			(pinfunction "MX3+_18")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14811,7 +14811,7 @@
 			(at -0.4953 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DC_N")
+			(net "/RGMII1/PHY1_DC_N")
 			(pinfunction "MX2-_19")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14821,7 +14821,7 @@
 			(at -1.4859 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DC_P")
+			(net "/RGMII1/PHY1_DC_P")
 			(pinfunction "MX2+_20")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14851,7 +14851,7 @@
 			(at -4.4577 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DD_N")
+			(net "/RGMII1/PHY1_DD_N")
 			(pinfunction "MX1-_23")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -14861,7 +14861,7 @@
 			(at -5.4483 -4.699 270)
 			(size 0.635 2.032)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_DD_P")
+			(net "/RGMII1/PHY1_DD_P")
 			(pinfunction "MX1+_24")
 			(pintype "passive")
 			(solder_paste_margin -0.02465)
@@ -15433,7 +15433,7 @@
 			(at 0 0 180)
 			(size 0.635 0.635)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_CLKO")
+			(net "/RGMII1/PHY1_CLKO")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -1)
@@ -17880,7 +17880,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DA_P")
+			(net "/RGMII0/PHY0_DA_P")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17892,7 +17892,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DA_N")
+			(net "/RGMII0/PHY0_DA_N")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17904,7 +17904,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DB_P")
+			(net "/RGMII0/PHY0_DB_P")
 			(pinfunction "3_3")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17916,7 +17916,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DC_P")
+			(net "/RGMII0/PHY0_DC_P")
 			(pinfunction "4_4")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17928,7 +17928,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DC_N")
+			(net "/RGMII0/PHY0_DC_N")
 			(pinfunction "5_5")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17940,7 +17940,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DB_N")
+			(net "/RGMII0/PHY0_DB_N")
 			(pinfunction "6_6")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17952,7 +17952,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DD_P")
+			(net "/RGMII0/PHY0_DD_P")
 			(pinfunction "7_7")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -17964,7 +17964,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY0_DD_N")
+			(net "/RGMII0/PHY0_DD_N")
 			(pinfunction "8_8")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -18470,7 +18470,7 @@
 			(at 0.75 0 90)
 			(size 0.8 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_LED1")
+			(net "/RGMII0/PHY0_LED1")
 			(pinfunction "A_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02053)
@@ -19758,7 +19758,7 @@
 			(at 0.75 0 90)
 			(size 0.8 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_LED2")
+			(net "/RGMII0/PHY0_LED2")
 			(pinfunction "A_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02053)
@@ -20253,7 +20253,7 @@
 			(at 0.75 0 90)
 			(size 0.8 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY1 TI/PHY1_LED1")
+			(net "/RGMII1/PHY1_LED1")
 			(pinfunction "A_2")
 			(pintype "passive")
 			(solder_paste_margin -0.02053)
@@ -21710,7 +21710,7 @@
 			(at -3.4 -2.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_A_N")
+			(net "/RGMII0/PHY0_TD_A_N")
 			(pinfunction "TD_P_A_1")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21720,7 +21720,7 @@
 			(at -3.4 -2.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_A_P")
+			(net "/RGMII0/PHY0_TD_A_P")
 			(pinfunction "TD_M_A_2")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21740,7 +21740,7 @@
 			(at -3.4 -1.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_B_N")
+			(net "/RGMII0/PHY0_TD_B_N")
 			(pinfunction "TD_P_B_4")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21750,7 +21750,7 @@
 			(at -3.4 -0.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_B_P")
+			(net "/RGMII0/PHY0_TD_B_P")
 			(pinfunction "TD_M_B_5")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21770,7 +21770,7 @@
 			(at -3.4 0.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_C_N")
+			(net "/RGMII0/PHY0_TD_C_N")
 			(pinfunction "TD_P_C_7")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21780,7 +21780,7 @@
 			(at -3.4 0.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_C_P")
+			(net "/RGMII0/PHY0_TD_C_P")
 			(pinfunction "TD_M_C_8")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21800,7 +21800,7 @@
 			(at -3.4 1.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_D_N")
+			(net "/RGMII0/PHY0_TD_D_N")
 			(pinfunction "TD_P_D_10")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21811,7 +21811,7 @@
 			(at -3.4 2.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_TD_D_P")
+			(net "/RGMII0/PHY0_TD_D_P")
 			(pinfunction "TD_M_D_11")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21821,7 +21821,7 @@
 			(at -3.4 2.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RBIAS")
+			(net "/RGMII0/PHY0_RBIAS")
 			(pinfunction "RBIAS_12")
 			(pintype "passive")
 			(solder_mask_margin 0.075)
@@ -21841,7 +21841,7 @@
 			(at -2.25 3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_XO")
+			(net "/RGMII0/PHY0_XO")
 			(pinfunction "XO_14")
 			(pintype "passive")
 			(solder_mask_margin 0.075)
@@ -21851,7 +21851,7 @@
 			(at -1.75 3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_XI")
+			(net "/RGMII0/PHY0_XI")
 			(pinfunction "XI_15")
 			(pintype "passive")
 			(solder_mask_margin 0.075)
@@ -21861,7 +21861,7 @@
 			(at -1.25 3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_MDC")
+			(net "/RGMII0/PHY0_MDC")
 			(pinfunction "MDC_16")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -21871,7 +21871,7 @@
 			(at -0.75 3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_MDIO")
+			(net "/RGMII0/PHY0_MDIO")
 			(pinfunction "MDIO_17")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -21881,7 +21881,7 @@
 			(at -0.25 3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_CLK_OUT")
+			(net "/RGMII0/PHY0_CLK_OUT")
 			(pinfunction "CLK_OUT_18")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -21951,7 +21951,7 @@
 			(at 3.4 2.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_TX_D3")
+			(net "/RGMII0/PHY0_RGMII_TX_D3")
 			(pinfunction "TX_D3_25")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -21961,7 +21961,7 @@
 			(at 3.4 2.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_TX_D2")
+			(net "/RGMII0/PHY0_RGMII_TX_D2")
 			(pinfunction "TX_D2_26")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -21971,7 +21971,7 @@
 			(at 3.4 1.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_TX_D1")
+			(net "/RGMII0/PHY0_RGMII_TX_D1")
 			(pinfunction "SGMII_SIP/TX_D1_27")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -21981,7 +21981,7 @@
 			(at 3.4 1.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_TX_D0")
+			(net "/RGMII0/PHY0_RGMII_TX_D0")
 			(pinfunction "SGMII_SIN/TX_D0_28")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -21991,7 +21991,7 @@
 			(at 3.4 0.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_TX_CLK")
+			(net "/RGMII0/PHY0_RGMII_TX_CLK")
 			(pinfunction "GTX_CLK_29")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22021,7 +22021,7 @@
 			(at 3.4 -0.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_RX_CLK")
+			(net "/RGMII0/PHY0_RGMII_RX_CLK")
 			(pinfunction "RX_CLK_32")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22031,7 +22031,7 @@
 			(at 3.4 -1.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_RX_D0")
+			(net "/RGMII0/PHY0_RGMII_RX_D0")
 			(pinfunction "SGMII_COP/RX_D0_33")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22041,7 +22041,7 @@
 			(at 3.4 -1.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_RX_D1")
+			(net "/RGMII0/PHY0_RGMII_RX_D1")
 			(pinfunction "SGMII_CON/RX_D1_34")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22051,7 +22051,7 @@
 			(at 3.4 -2.25 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_RX_D2")
+			(net "/RGMII0/PHY0_RGMII_RX_D2")
 			(pinfunction "SGMII_SOP/RX_D2_35")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22061,7 +22061,7 @@
 			(at 3.4 -2.75 90)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_RX_D3")
+			(net "/RGMII0/PHY0_RGMII_RX_D3")
 			(pinfunction "SGMII_SON/RX_D3_36")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22071,7 +22071,7 @@
 			(at 2.75 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_TX_CTL")
+			(net "/RGMII0/PHY0_RGMII_TX_CTL")
 			(pinfunction "TX_CTRL_37")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22081,7 +22081,7 @@
 			(at 2.25 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RGMII_RX_CTL")
+			(net "/RGMII0/PHY0_RGMII_RX_CTL")
 			(pinfunction "RX_CTRL_38")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22091,7 +22091,7 @@
 			(at 1.75 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_GPIO0")
+			(net "/RGMII0/PHY0_GPIO0")
 			(pinfunction "GPIO_0_39")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22101,7 +22101,7 @@
 			(at 1.25 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_GPIO1")
+			(net "/RGMII0/PHY0_GPIO1")
 			(pinfunction "GPIO_1_40")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22132,7 +22132,7 @@
 			(at -0.25 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_RESET#")
+			(net "/RGMII0/PHY0_RESET#")
 			(pinfunction "~{RESET}_43")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22142,7 +22142,7 @@
 			(at -0.75 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_INTN")
+			(net "/RGMII0/PHY0_INTN")
 			(pinfunction "INT/PWDN_44")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22152,7 +22152,7 @@
 			(at -1.25 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_LED2")
+			(net "/RGMII0/PHY0_LED2")
 			(pinfunction "LED_2_45")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22162,7 +22162,7 @@
 			(at -1.75 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_LED1")
+			(net "/RGMII0/PHY0_LED1")
 			(pinfunction "LED_1_46")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22172,7 +22172,7 @@
 			(at -2.25 -3.4)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "PHY0_LED0")
+			(net "/RGMII0/PHY0_LED0")
 			(pinfunction "LED_0_47")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22708,7 +22708,7 @@
 			(at -3.4 -2.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_A_N")
+			(net "/RGMII0/PHY0_TD_A_N")
 			(pinfunction "TD_P_A_1")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22718,7 +22718,7 @@
 			(at -3.4 -2.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_A_P")
+			(net "/RGMII0/PHY0_TD_A_P")
 			(pinfunction "TD_M_A_2")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22738,7 +22738,7 @@
 			(at -3.4 -1.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_B_N")
+			(net "/RGMII0/PHY0_TD_B_N")
 			(pinfunction "TD_P_B_4")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22748,7 +22748,7 @@
 			(at -3.4 -0.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_B_P")
+			(net "/RGMII0/PHY0_TD_B_P")
 			(pinfunction "TD_M_B_5")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22768,7 +22768,7 @@
 			(at -3.4 0.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_C_N")
+			(net "/RGMII0/PHY0_TD_C_N")
 			(pinfunction "TD_P_C_7")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22778,7 +22778,7 @@
 			(at -3.4 0.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_C_P")
+			(net "/RGMII0/PHY0_TD_C_P")
 			(pinfunction "TD_M_C_8")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22798,7 +22798,7 @@
 			(at -3.4 1.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_D_N")
+			(net "/RGMII0/PHY0_TD_D_N")
 			(pinfunction "TD_P_D_10")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22809,7 +22809,7 @@
 			(at -3.4 2.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_TD_D_P")
+			(net "/RGMII0/PHY0_TD_D_P")
 			(pinfunction "TD_M_D_11")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22819,7 +22819,7 @@
 			(at -3.4 2.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RBIAS")
+			(net "/RGMII0/PHY0_RBIAS")
 			(pinfunction "RBIAS_12")
 			(pintype "passive")
 			(solder_mask_margin 0.075)
@@ -22839,7 +22839,7 @@
 			(at -2.25 3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_XO")
+			(net "/RGMII0/PHY0_XO")
 			(pinfunction "XO_14")
 			(pintype "passive")
 			(solder_mask_margin 0.075)
@@ -22849,7 +22849,7 @@
 			(at -1.75 3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_XI")
+			(net "/RGMII0/PHY0_XI")
 			(pinfunction "XI_15")
 			(pintype "passive")
 			(solder_mask_margin 0.075)
@@ -22859,7 +22859,7 @@
 			(at -1.25 3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_MDC")
+			(net "/RGMII0/PHY0_MDC")
 			(pinfunction "MDC_16")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22869,7 +22869,7 @@
 			(at -0.75 3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_MDIO")
+			(net "/RGMII0/PHY0_MDIO")
 			(pinfunction "MDIO_17")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -22879,7 +22879,7 @@
 			(at -0.25 3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_CLK_OUT")
+			(net "/RGMII0/PHY0_CLK_OUT")
 			(pinfunction "CLK_OUT_18")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -22949,7 +22949,7 @@
 			(at 3.4 2.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_TX_D3")
+			(net "/RGMII0/PHY0_RGMII_TX_D3")
 			(pinfunction "TX_D3_25")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22959,7 +22959,7 @@
 			(at 3.4 2.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_TX_D2")
+			(net "/RGMII0/PHY0_RGMII_TX_D2")
 			(pinfunction "TX_D2_26")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22969,7 +22969,7 @@
 			(at 3.4 1.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_TX_D1")
+			(net "/RGMII0/PHY0_RGMII_TX_D1")
 			(pinfunction "SGMII_SIP/TX_D1_27")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22979,7 +22979,7 @@
 			(at 3.4 1.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_TX_D0")
+			(net "/RGMII0/PHY0_RGMII_TX_D0")
 			(pinfunction "SGMII_SIN/TX_D0_28")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -22989,7 +22989,7 @@
 			(at 3.4 0.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_TX_CLK")
+			(net "/RGMII0/PHY0_RGMII_TX_CLK")
 			(pinfunction "GTX_CLK_29")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -23019,7 +23019,7 @@
 			(at 3.4 -0.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_RX_CLK")
+			(net "/RGMII0/PHY0_RGMII_RX_CLK")
 			(pinfunction "RX_CLK_32")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23029,7 +23029,7 @@
 			(at 3.4 -1.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_RX_D0")
+			(net "/RGMII0/PHY0_RGMII_RX_D0")
 			(pinfunction "SGMII_COP/RX_D0_33")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23039,7 +23039,7 @@
 			(at 3.4 -1.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_RX_D1")
+			(net "/RGMII0/PHY0_RGMII_RX_D1")
 			(pinfunction "SGMII_CON/RX_D1_34")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23049,7 +23049,7 @@
 			(at 3.4 -2.25 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_RX_D2")
+			(net "/RGMII0/PHY0_RGMII_RX_D2")
 			(pinfunction "SGMII_SOP/RX_D2_35")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23059,7 +23059,7 @@
 			(at 3.4 -2.75 270)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_RX_D3")
+			(net "/RGMII0/PHY0_RGMII_RX_D3")
 			(pinfunction "SGMII_SON/RX_D3_36")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23069,7 +23069,7 @@
 			(at 2.75 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_TX_CTL")
+			(net "/RGMII0/PHY0_RGMII_TX_CTL")
 			(pinfunction "TX_CTRL_37")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -23079,7 +23079,7 @@
 			(at 2.25 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RGMII_RX_CTL")
+			(net "/RGMII0/PHY0_RGMII_RX_CTL")
 			(pinfunction "RX_CTRL_38")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -23089,7 +23089,7 @@
 			(at 1.75 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_GPIO0")
+			(net "/RGMII0/PHY0_GPIO0")
 			(pinfunction "GPIO_0_39")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23099,7 +23099,7 @@
 			(at 1.25 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_GPIO1")
+			(net "/RGMII0/PHY0_GPIO1")
 			(pinfunction "GPIO_1_40")
 			(pintype "output")
 			(solder_mask_margin 0.075)
@@ -23130,7 +23130,7 @@
 			(at -0.25 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_RESET#")
+			(net "/RGMII0/PHY0_RESET#")
 			(pinfunction "~{RESET}_43")
 			(pintype "input")
 			(solder_mask_margin 0.075)
@@ -23140,7 +23140,7 @@
 			(at -0.75 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_INTN")
+			(net "/RGMII0/PHY0_INTN")
 			(pinfunction "INT/PWDN_44")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -23150,7 +23150,7 @@
 			(at -1.25 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_LED2")
+			(net "/RGMII0/PHY0_LED2")
 			(pinfunction "LED_2_45")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -23160,7 +23160,7 @@
 			(at -1.75 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_LED1")
+			(net "/RGMII0/PHY0_LED1")
 			(pinfunction "LED_1_46")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -23170,7 +23170,7 @@
 			(at -2.25 -3.4 180)
 			(size 0.25 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_LED0")
+			(net "/RGMII0/PHY0_LED0")
 			(pinfunction "LED_0_47")
 			(pintype "bidirectional")
 			(solder_mask_margin 0.075)
@@ -24663,7 +24663,7 @@
 			(at -1.15 0.925 180)
 			(size 1.3 1.05)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_XI")
+			(net "/RGMII0/PHY0_XI")
 			(pinfunction "OSC1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.0298)
@@ -24683,7 +24683,7 @@
 			(at 1.15 -0.925 180)
 			(size 1.3 1.05)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/PHY0 TI/PHY0_XO")
+			(net "/RGMII0/PHY0_XO")
 			(pinfunction "OSC2_3")
 			(pintype "passive")
 			(solder_paste_margin -0.0298)
@@ -27372,7 +27372,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DA_P")
+			(net "/RGMII1/PHY1_DA_P")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27384,7 +27384,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DA_N")
+			(net "/RGMII1/PHY1_DA_N")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27396,7 +27396,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DB_P")
+			(net "/RGMII1/PHY1_DB_P")
 			(pinfunction "3_3")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27408,7 +27408,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DC_P")
+			(net "/RGMII1/PHY1_DC_P")
 			(pinfunction "4_4")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27420,7 +27420,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DC_N")
+			(net "/RGMII1/PHY1_DC_N")
 			(pinfunction "5_5")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27432,7 +27432,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DB_N")
+			(net "/RGMII1/PHY1_DB_N")
 			(pinfunction "6_6")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27444,7 +27444,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DD_P")
+			(net "/RGMII1/PHY1_DD_P")
 			(pinfunction "7_7")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -27456,7 +27456,7 @@
 			(drill 0.89)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net "PHY1_DD_N")
+			(net "/RGMII1/PHY1_DD_N")
 			(pinfunction "8_8")
 			(pintype "passive")
 			(thermal_bridge_angle 90)
@@ -29748,7 +29748,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "/PHY0 TI/PHY0_RESET#")
+			(net "/RGMII0/PHY0_RESET#")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -30609,7 +30609,6 @@
 			)
 		)
 		(property ki_fp_filters "*CAPC1005X50*")
-		(path "/c312d489-45ac-469c-8828-bd0c551aa130")
 		(sheetname "/RGMII2/")
 		(sheetfile "rgmii2.kicad_sch")
 		(units
@@ -38201,7 +38200,6 @@
 			)
 		)
 		(property ki_fp_filters "*CAPC1005X50*")
-		(path "/3eb7b852-e31c-4b07-b1dd-a2ae8bf6634b")
 		(sheetname "/RGMII2/")
 		(sheetfile "rgmii2.kicad_sch")
 		(units
@@ -40013,7 +40011,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "/PHY1 TI/PHY1_INTN")
+			(net "/RGMII1/PHY1_INTN")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -42380,7 +42378,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY1_MDIO")
+			(net "/RGMII1/PHY1_MDIO")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -44761,7 +44759,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY0_RGMII_RX_CTL")
+			(net "/RGMII0/PHY0_RGMII_RX_CTL")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -57274,7 +57272,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY1_INTN")
+			(net "/RGMII1/PHY1_INTN")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -63004,7 +63002,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "/PHY1 TI/PHY1_RGMII_RX_CTL")
+			(net "/RGMII1/PHY1_RGMII_RX_CTL")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -67770,7 +67768,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY1_RGMII_RX_CTL")
+			(net "/RGMII1/PHY1_RGMII_RX_CTL")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -69068,7 +69066,6 @@
 			)
 		)
 		(property ki_fp_filters "*CAPC1005X50*")
-		(path "/fd91db2e-86ee-452f-9a72-2c1333cb2b33")
 		(sheetname "/RGMII2/")
 		(sheetfile "rgmii2.kicad_sch")
 		(units
@@ -69524,7 +69521,6 @@
 			)
 		)
 		(property ki_fp_filters "*CAPC1005X50*")
-		(path "/d25c2218-54b2-4654-95ae-e52dc6dfb4ab")
 		(sheetname "/RGMII2/")
 		(sheetfile "rgmii2.kicad_sch")
 		(units
@@ -77359,7 +77355,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY1_RESET#")
+			(net "/RGMII1/PHY1_RESET#")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -79302,7 +79298,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "/PHY1 TI/PHY1_MDIO")
+			(net "/RGMII1/PHY1_MDIO")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -85520,7 +85516,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY0_RGMII_RX_CTL")
+			(net "/RGMII0/PHY0_RGMII_RX_CTL")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -89607,7 +89603,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "/PHY1 TI/PHY1_RESET#")
+			(net "/RGMII1/PHY1_RESET#")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -92152,7 +92148,6 @@
 			)
 		)
 		(property ki_fp_filters "*RESC1005X40*")
-		(path "/7b2f3ea4-a8be-45d7-9f74-891a7eb988e3")
 		(sheetname "/RGMII2/")
 		(sheetfile "rgmii2.kicad_sch")
 		(units
@@ -92258,7 +92253,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "/RGMII2/CONF_DONE")
+			(net "/Expansion/CONF_DONE")
 			(pinfunction "2_2")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -92645,7 +92640,6 @@
 			)
 		)
 		(property ki_fp_filters "*CAPC1005X50*")
-		(path "/2be97ba0-a940-47fd-a77f-ec636d6ec6ee")
 		(sheetname "/RGMII2/")
 		(sheetfile "rgmii2.kicad_sch")
 		(units
@@ -95801,7 +95795,7 @@
 			(size 0.6 0.55)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.075)
-			(net "PHY0_RBIAS")
+			(net "/RGMII0/PHY0_RBIAS")
 			(pinfunction "1_1")
 			(pintype "passive")
 			(solder_paste_margin -0.01473)
@@ -99362,14 +99356,6 @@
 		)
 	)
 	(segment
-		(start 151.8856 89.4191)
-		(end 151.8856 89.4191)
-		(width 0.127)
-		(layer "F.Cu")
-		(net "")
-		(uuid "009ffcf0-741b-4995-9017-508663d9d660")
-	)
-	(segment
 		(start 168.93523 121.8716)
 		(end 169.0231 121.78373)
 		(width 0.15)
@@ -99450,14 +99436,6 @@
 		(uuid "0bb57cde-1e1b-496d-b8c1-e4410cd16db6")
 	)
 	(segment
-		(start 166.0579 102.7654)
-		(end 167.0261 103.7336)
-		(width 0.127)
-		(layer "F.Cu")
-		(net "")
-		(uuid "0d197870-ef6c-4d92-8e50-0c4b6daac0fc")
-	)
-	(segment
 		(start 139.0791 84.6156)
 		(end 139.0791 84.6155)
 		(width 0.127)
@@ -99474,14 +99452,6 @@
 		(uuid "0dbc7b7e-fd5e-43c0-8327-ec2c80807aa0")
 	)
 	(segment
-		(start 155.1011 93.4036)
-		(end 156.6011 91.9036)
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 		(covering
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@@ -114476,11 +114540,11 @@
 			(back no)
 		)
 		(filling no)
-		(net "/PHY0 TI/PHY0_RGMII_RX_CTL")
-		(uuid "b123bcaf-3a19-4e5c-85a5-eaa372ebe2fe")
+		(net "/RGMII0/PHY0_GPIO0")
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 		(layers "F.Cu" "B.Cu")
@@ -114494,77 +114558,131 @@
 			(back no)
 		)
 		(filling no)
-		(net "/PHY0 TI/PHY0_RGMII_RX_CTL")
-		(uuid "e53fc51b-aed2-4e61-82c0-126ace4aba99")
+		(net "/RGMII0/PHY0_GPIO0")
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@@ -114578,805 +114696,965 @@
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 		(layer "B.Cu")
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