From 7b1b5e7eb712d41888398934834cae730e0aa5a0 Mon Sep 17 00:00:00 2001 From: Private Island Networks Inc Date: Sun, 21 Dec 2025 20:51:04 -0500 Subject: betsy: preliminary beta snapshot --- src/sync_fifo.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'src/sync_fifo.v') diff --git a/src/sync_fifo.v b/src/sync_fifo.v index 56c83d4..52c15cd 100644 --- a/src/sync_fifo.v +++ b/src/sync_fifo.v @@ -1,6 +1,7 @@ /* - * sync_fifo.v + * sync_fifo.v * + * Copyright (C) 2025 Private Island Networks Inc. * Copyright (C) 2018, 2019 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,8 +20,6 @@ * */ -`timescale 1ns /10ps - module sync_fifo #(parameter FIFO_PTR = 11, FIFO_WIDTH = 9, FIFO_DEPTH = 2048 ) @@ -47,7 +46,9 @@ module sync_fifo #(parameter FIFO_PTR = 11, ); +`define INCLUDED `include "ethernet_params.v" +`undef INCLUDED reg [FIFO_PTR-1:0] wr_ptr; reg [FIFO_PTR-1:0] rd_ptr; @@ -60,7 +61,7 @@ always @(posedge clk, negedge rstn) else if ( reset_ptrs ) wr_ptr <= 'd0; else if ( we ) - wr_ptr <= wr_ptr + 1; + wr_ptr <= wr_ptr + 1'b1; /* * rd_ptr @@ -72,7 +73,7 @@ always @(posedge clk, negedge rstn) else if ( reset_ptrs ) rd_ptr <= 'd0; else if ( re && !empty ) - rd_ptr <= rd_ptr + 1; + rd_ptr <= rd_ptr + 1'b1; assign empty = ( rd_ptr == wr_ptr ) ? 1'b1 : 1'b0; assign almost_full = wr_bytes_available < MTU ? 1'b1 : 1'b0; @@ -88,7 +89,7 @@ always @(posedge clk, negedge rstn) assign active = ~empty; -dpram dpram_fifo( +dpram_inf dpram_fifo( .rstn( rstn ), .a_clk( clk ), .a_clk_e( 1'b1 ), -- cgit v1.2.3-8-gadcc