From 6e969b02b4f6266bb9af926bfba6698468c74c28 Mon Sep 17 00:00:00 2001
From: mindchasers <privateisland@mindchasers.com>
Date: Mon, 16 Nov 2020 17:10:41 -0500
Subject: project: rename device to lattice to include specific manufacturers

---
 .../lattice/ecp5um/boards/darsena/darsena.sty      | 201 +++++++++++++++++++++
 .../lattice/ecp5um/boards/darsena/darsena_v02.lpf  | 154 ++++++++++++++++
 .../lattice/ecp5um/boards/darsena/labs.rva         | 137 ++++++++++++++
 .../lattice/ecp5um/boards/darsena/labs.rvl         | 107 +++++++++++
 .../lattice/ecp5um/boards/darsena/labs.rvs         | 102 +++++++++++
 5 files changed, 701 insertions(+)
 create mode 100644 manufacturer/lattice/ecp5um/boards/darsena/darsena.sty
 create mode 100644 manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf
 create mode 100644 manufacturer/lattice/ecp5um/boards/darsena/labs.rva
 create mode 100644 manufacturer/lattice/ecp5um/boards/darsena/labs.rvl
 create mode 100644 manufacturer/lattice/ecp5um/boards/darsena/labs.rvs

(limited to 'manufacturer/lattice/ecp5um/boards')

diff --git a/manufacturer/lattice/ecp5um/boards/darsena/darsena.sty b/manufacturer/lattice/ecp5um/boards/darsena/darsena.sty
new file mode 100644
index 0000000..b9a247b
--- /dev/null
+++ b/manufacturer/lattice/ecp5um/boards/darsena/darsena.sty
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="CmdLineArgs" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="5" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="False" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="True" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="2" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="1" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="125" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="10" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="20" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="Verilog" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="Yes" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>
diff --git a/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf b/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf
new file mode 100644
index 0000000..98c999b
--- /dev/null
+++ b/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf
@@ -0,0 +1,154 @@
+rvl_alias "clk_10" "clk_10";
+RVL_ALIAS "refclko" "refclko"; 
+RVL_ALIAS "refclko" "refclko"; 
+RVL_ALIAS "refclko" "refclko"; 
+#########################################
+# 			versa.lpf
+#########################################
+FREQUENCY 125.000000 MHz;
+FREQUENCY NET "pcs_pclk" 125.000000 MHz PAR_ADJ 25.000000 ;
+FREQUENCY NET "clk_10_0" 9.700000 MHz ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BANK 0 VCCIO 3.3 V;
+BANK 1 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+BANK 3 VCCIO 3.3 V;
+BANK 6 VCCIO 3.3 V;
+BANK 7 VCCIO 3.3 V;
+BANK 8 VCCIO 3.3 V;
+#########################################
+# 			I/O Pin Assignemnts:
+#########################################
+// Micro
+LOCATE COMP "rstn" SITE "F1" ;// GSRN ping
+LOCATE COMP "i2c_scl" SITE "B1" ;
+LOCATE COMP "i2c_sda" SITE "C1" ;
+LOCATE COMP "fpga_spics" SITE "H1" ;
+LOCATE COMP "fpga_mclk" SITE "H2" ;
+LOCATE COMP "fpga_mosi" SITE "G1" ;
+LOCATE COMP "fpga_miso" SITE "F2" ;
+LOCATE COMP "fpga_int" SITE "E2" ;
+LOCATE COMP "uart_txd" SITE "D2" ;
+LOCATE COMP "uart_rxd" SITE "E1" ;
+LOCATE COMP "led[0]" SITE "P20" ;
+LOCATE COMP "led[1]" SITE "M20" ;
+LOCATE COMP "led[2]" SITE "M19" ;
+// PHY
+LOCATE COMP "phy_mdc" SITE "J1" ;
+// PHY0
+LOCATE COMP "phy0_resetn" SITE "K2" ;
+LOCATE COMP "phy0_mdio" SITE "L2" ;
+LOCATE COMP "phy0_intn" SITE "K1" ;
+LOCATE COMP "phy0_gpio[0]" SITE "M1" ;
+LOCATE COMP "phy0_gpio[1]" SITE "L1" ;
+// PHY1
+LOCATE COMP "phy1_resetn" SITE "N20" ;
+LOCATE COMP "phy1_mdio" SITE "U20" ;
+LOCATE COMP "phy1_intn" SITE "U19" ;
+LOCATE COMP "phy1_gpio[0]" SITE "R20" ;
+LOCATE COMP "phy1_gpio[1]" SITE "P19" ;
+
+// Arduino Expansion
+LOCATE COMP "ard_sda" SITE "A19" ;
+LOCATE COMP "ard_scl" SITE "B20" ;
+LOCATE COMP "ard_rxd1" SITE "A18" ;
+LOCATE COMP "ard_rxd2" SITE "A14" ;
+LOCATE COMP "ard_rxd3" SITE "A7" ;
+LOCATE COMP "ard_txd1" SITE "A17" ;
+LOCATE COMP "ard_txd2" SITE "A10" ;
+LOCATE COMP "ard_txd3" SITE "A6" ;
+LOCATE COMP "pe0" SITE "A5" ;
+LOCATE COMP "pe1" SITE "B5" ;
+LOCATE COMP "pe3" SITE "B3" ;
+LOCATE COMP "pe4" SITE "A4" ;
+LOCATE COMP "pe5" SITE "B4" ;
+LOCATE COMP "pg5" SITE "A3" ;
+LOCATE COMP "ph3" SITE "A2" ;
+LOCATE COMP "ph4" SITE "B2" ;
+
+// PHY2
+
+LOCATE COMP "phy2_mdc" SITE "C20" ;
+LOCATE COMP "phy2_mdio" SITE "D19" ;
+LOCATE COMP "phy2_resetn" SITE "D20" ;
+
+//LOCATE COMP "pa[0]" SITE "C20" ;
+//LOCATE COMP "pa[1]" SITE "D19" ;
+//LOCATE COMP "pa[2]" SITE "D20" ;
+LOCATE COMP "pa[3]" SITE "E19" ;
+LOCATE COMP "pa[4]" SITE "E20" ;
+LOCATE COMP "pa[5]" SITE "F19" ;
+LOCATE COMP "pa[6]" SITE "F20" ;
+LOCATE COMP "pa[7]" SITE "G20" ;
+LOCATE COMP "pa[8]" SITE "G19" ;
+LOCATE COMP "pa[9]" SITE "H20" ;
+
+
+// V02
+LOCATE COMP "ftdi_tck_txd" SITE "R1" ;
+LOCATE COMP "ftdi_tdi_rxd" SITE "T1" ;
+LOCATE COMP "fpga_jtag_e" SITE "V1" ;
+LOCATE COMP "fpga_gpio" SITE "N1" ;
+IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "uart_rxd" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 OPENDRAIN=ON DRIVE=16 SLEWRATE=FAST ;
+SYSCONFIG CONFIG_IOVOLTAGE=3.3 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE CONFIG_MODE=JTAG BACKGROUND_RECONFIG=OFF ;
+VOLTAGE 1.045 V;
+USERCODE BIN "00000000000000000000000000000000" ; 
+BLOCK JTAGPATHS ;
+IOBUF PORT "rstn" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy2_mdc" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_int" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy2_resetn" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy0_resetn" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy1_resetn" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "led[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "led[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "led[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "phy2_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ;
+IOBUF PORT "phy0_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP OPENDRAIN=OFF ;
+IOBUF PORT "phy1_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ;
+IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ard_rxd1" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "ard_rxd2" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ard_rxd3" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "ard_txd1" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ard_txd2" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ard_txd3" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy_mdc" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "pe0" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pe1" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pe3" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pe4" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pe5" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pg5" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ph3" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ph4" IO_TYPE=LVCMOS33 ;
+
+//IOBUF PORT "pa[0]" IO_TYPE=LVCMOS33 ;
+//IOBUF PORT "pa[1]" IO_TYPE=LVCMOS33 ;
+//IOBUF PORT "pa[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[4]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[5]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[6]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[7]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "pa[9]" IO_TYPE=LVCMOS33 ;
+
+# V02
+IOBUF PORT "ftdi_tck_txd" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ftdi_tdi_rxd" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_jtag_e" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_gpio" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy1_intn" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "phy0_intn" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_mclk" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_spics" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "fpga_mosi" IO_TYPE=LVCMOS33 ;
diff --git a/manufacturer/lattice/ecp5um/boards/darsena/labs.rva b/manufacturer/lattice/ecp5um/boards/darsena/labs.rva
new file mode 100644
index 0000000..92b5eb8
--- /dev/null
+++ b/manufacturer/lattice/ecp5um/boards/darsena/labs.rva
@@ -0,0 +1,137 @@
+<!DOCTYPE ispTLA>
+<ispTLA>
+ <CreationDate>Mon Jul 8 17:47:16 2019</CreationDate>
+ <XCFFileName/>
+ <CableSetting>
+  <IsTRSTConnected val="false"/>
+  <TRSTSetting val="0"/>
+  <IsBSCANConnected val="false"/>
+  <BSCANSetting val="0"/>
+  <CableType val="USB2"/>
+  <PortAddress val="0"/>
+  <PortSetting val="0"/>
+  <TCKDelay val="1"/>
+ </CableSetting>
+ <DeviceCount>1</DeviceCount>
+ <Device>
+  <DeviceIndex>0</DeviceIndex>
+  <DeviceName>1. LFE5UM-45F</DeviceName>
+  <DeviceID>0x01112043</DeviceID>
+  <HasIspTRACY>true</HasIspTRACY>
+  <HasJTAG2WB>false</HasJTAG2WB>
+  <SERDES/>
+  <IRBypassLen>8</IRBypassLen>
+  <RVLFileName>labs.rvl</RVLFileName>
+  <RVSFileName>labs.rvs</RVSFileName>
+  <LACoreCount>1</LACoreCount>
+  <WinUI CoreIndex="0">
+   <TraceSigTreeData>
+    <TraceSignal IsHidden="false" Name="TU1" NodeType="0" PortIndex="71"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/scl_i" NodeType="0" PortIndex="0"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/scl_i_m1" NodeType="0" PortIndex="1"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/scl_i_m2" NodeType="0" PortIndex="2"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/scl_high" NodeType="0" PortIndex="3"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/scl_low" NodeType="0" PortIndex="4"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/sda_i" NodeType="0" PortIndex="5"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/sda_i_m1" NodeType="0" PortIndex="6"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/start" NodeType="0" PortIndex="7"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/stop" NodeType="0" PortIndex="8"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/run" NodeType="0" PortIndex="9"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/bit_cnt" NodeType="1" PortIndex="10">
+     <BusRadix Radix="2"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/bit_cnt:0" NodeType="2" PortIndex="10"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/bit_cnt:1" NodeType="2" PortIndex="11"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/bit_cnt:2" NodeType="2" PortIndex="12"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/bit_cnt:3" NodeType="2" PortIndex="13"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/bit_cnt:4" NodeType="2" PortIndex="14"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad" NodeType="1" PortIndex="15">
+     <BusRadix Radix="3"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:0" NodeType="2" PortIndex="15"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:1" NodeType="2" PortIndex="16"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:2" NodeType="2" PortIndex="17"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:3" NodeType="2" PortIndex="18"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:4" NodeType="2" PortIndex="19"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:5" NodeType="2" PortIndex="20"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/dev_ad:6" NodeType="2" PortIndex="21"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr" NodeType="1" PortIndex="22">
+     <BusRadix Radix="3"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:0" NodeType="2" PortIndex="22"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:1" NodeType="2" PortIndex="23"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:2" NodeType="2" PortIndex="24"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:3" NodeType="2" PortIndex="25"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:4" NodeType="2" PortIndex="26"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:5" NodeType="2" PortIndex="27"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:6" NodeType="2" PortIndex="28"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/addr:7" NodeType="2" PortIndex="29"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d" NodeType="1" PortIndex="30">
+     <BusRadix Radix="3"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:0" NodeType="2" PortIndex="30"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:1" NodeType="2" PortIndex="31"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:2" NodeType="2" PortIndex="32"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:3" NodeType="2" PortIndex="33"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:4" NodeType="2" PortIndex="34"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:5" NodeType="2" PortIndex="35"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:6" NodeType="2" PortIndex="36"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/d:7" NodeType="2" PortIndex="37"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/ack" NodeType="0" PortIndex="38"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/rwn" NodeType="0" PortIndex="39"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/cont_sel" NodeType="0" PortIndex="40"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/cont_done" NodeType="0" PortIndex="41"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di" NodeType="1" PortIndex="42">
+     <BusRadix Radix="3"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:0" NodeType="2" PortIndex="42"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:1" NodeType="2" PortIndex="43"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:2" NodeType="2" PortIndex="44"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:3" NodeType="2" PortIndex="45"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:4" NodeType="2" PortIndex="46"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:5" NodeType="2" PortIndex="47"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_di:6" NodeType="2" PortIndex="48"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_we" NodeType="0" PortIndex="49"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/cont_we" NodeType="0" PortIndex="50"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do" NodeType="1" PortIndex="51">
+     <BusRadix Radix="3"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:0" NodeType="2" PortIndex="51"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:1" NodeType="2" PortIndex="52"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:2" NodeType="2" PortIndex="53"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:3" NodeType="2" PortIndex="54"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:4" NodeType="2" PortIndex="55"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:5" NodeType="2" PortIndex="56"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:6" NodeType="2" PortIndex="57"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/mem_do:7" NodeType="2" PortIndex="58"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/fifo_re" NodeType="0" PortIndex="59"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di" NodeType="1" PortIndex="60">
+     <BusRadix Radix="3"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:0" NodeType="2" PortIndex="60"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:1" NodeType="2" PortIndex="61"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:2" NodeType="2" PortIndex="62"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:3" NodeType="2" PortIndex="63"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:4" NodeType="2" PortIndex="64"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:5" NodeType="2" PortIndex="65"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:6" NodeType="2" PortIndex="66"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/i_di:7" NodeType="2" PortIndex="67"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/sda_o" NodeType="0" PortIndex="68"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/sda_oe" NodeType="0" PortIndex="69"/>
+    <TraceSignal IsHidden="false" Name="i2c_0/tx_fifo_empty" NodeType="0" PortIndex="70"/>
+   </TraceSigTreeData>
+   <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
+   <CoreRun Run="true"/>
+   <CoreWndUIData>
+    <ClockFrequency Unit="ns" Frequency="-1.0"/>
+   </CoreWndUIData>
+  </WinUI>
+ </Device>
+</ispTLA>
diff --git a/manufacturer/lattice/ecp5um/boards/darsena/labs.rvl b/manufacturer/lattice/ecp5um/boards/darsena/labs.rvl
new file mode 100644
index 0000000..ad00f8e
--- /dev/null
+++ b/manufacturer/lattice/ecp5um/boards/darsena/labs.rvl
@@ -0,0 +1,107 @@
+<Project ModBy="Inserter" SigType="0" Name="C:/projects/lattice/privateisland/boards/darsena/labs.rvl" Date="2019-07-08">
+    <IP Version="1_6_042617"/>
+    <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="ECP5UM" DesignName="privateisland"/>
+    <Core InsertDataset="0" Insert="1" Reveal_sig="231808093" Name="lab_1_i2c" ID="0">
+        <Setting>
+            <Clock SampleClk="clk_10" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="2048"/>
+            <Capture Mode="0" MinSamplesPerTrig="8"/>
+            <Event CntEnable="0" MaxEventCnt="8"/>
+            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_top_LA0_net"/>
+            <DistRAM Disable="0"/>
+        </Setting>
+        <Dataset Name="Base">
+            <Trace>
+                <Sig Type="SIG" Name="i2c_0/scl_i"/>
+                <Sig Type="SIG" Name="i2c_0/scl_i_m1"/>
+                <Sig Type="SIG" Name="i2c_0/scl_i_m2"/>
+                <Sig Type="SIG" Name="i2c_0/scl_high"/>
+                <Sig Type="SIG" Name="i2c_0/scl_low"/>
+                <Sig Type="SIG" Name="i2c_0/sda_i"/>
+                <Sig Type="SIG" Name="i2c_0/sda_i_m1"/>
+                <Sig Type="SIG" Name="i2c_0/start"/>
+                <Sig Type="SIG" Name="i2c_0/stop"/>
+                <Sig Type="SIG" Name="i2c_0/run"/>
+                <Bus Name="i2c_0/bit_cnt">
+                    <Sig Type="SIG" Name="i2c_0/bit_cnt:0"/>
+                    <Sig Type="SIG" Name="i2c_0/bit_cnt:1"/>
+                    <Sig Type="SIG" Name="i2c_0/bit_cnt:2"/>
+                    <Sig Type="SIG" Name="i2c_0/bit_cnt:3"/>
+                    <Sig Type="SIG" Name="i2c_0/bit_cnt:4"/>
+                </Bus>
+                <Bus Name="i2c_0/dev_ad">
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:0"/>
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:1"/>
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:2"/>
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:3"/>
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:4"/>
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:5"/>
+                    <Sig Type="SIG" Name="i2c_0/dev_ad:6"/>
+                </Bus>
+                <Bus Name="i2c_0/addr">
+                    <Sig Type="SIG" Name="i2c_0/addr:0"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:1"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:2"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:3"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:4"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:5"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:6"/>
+                    <Sig Type="SIG" Name="i2c_0/addr:7"/>
+                </Bus>
+                <Bus Name="i2c_0/d">
+                    <Sig Type="SIG" Name="i2c_0/d:0"/>
+                    <Sig Type="SIG" Name="i2c_0/d:1"/>
+                    <Sig Type="SIG" Name="i2c_0/d:2"/>
+                    <Sig Type="SIG" Name="i2c_0/d:3"/>
+                    <Sig Type="SIG" Name="i2c_0/d:4"/>
+                    <Sig Type="SIG" Name="i2c_0/d:5"/>
+                    <Sig Type="SIG" Name="i2c_0/d:6"/>
+                    <Sig Type="SIG" Name="i2c_0/d:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="i2c_0/ack"/>
+                <Sig Type="SIG" Name="i2c_0/rwn"/>
+                <Sig Type="SIG" Name="i2c_0/cont_sel"/>
+                <Sig Type="SIG" Name="i2c_0/cont_done"/>
+                <Bus Name="i2c_0/fifo_di">
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:0"/>
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:1"/>
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:2"/>
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:3"/>
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:4"/>
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:5"/>
+                    <Sig Type="SIG" Name="i2c_0/fifo_di:6"/>
+                </Bus>
+                <Sig Type="SIG" Name="i2c_0/mem_we"/>
+                <Sig Type="SIG" Name="i2c_0/cont_we"/>
+                <Bus Name="i2c_0/mem_do">
+                    <Sig Type="SIG" Name="i2c_0/mem_do:0"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:1"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:2"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:3"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:4"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:5"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:6"/>
+                    <Sig Type="SIG" Name="i2c_0/mem_do:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="i2c_0/fifo_re"/>
+                <Bus Name="i2c_0/i_di">
+                    <Sig Type="SIG" Name="i2c_0/i_di:0"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:1"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:2"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:3"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:4"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:5"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:6"/>
+                    <Sig Type="SIG" Name="i2c_0/i_di:7"/>
+                </Bus>
+                <Sig Type="SIG" Name="i2c_0/sda_o"/>
+                <Sig Type="SIG" Name="i2c_0/sda_oe"/>
+                <Sig Type="SIG" Name="i2c_0/tx_fifo_empty"/>
+            </Trace>
+            <Trigger>
+                <TU Serialbits="0" Type="0" ID="1" Sig="i2c_0/start,"/>
+                <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
+            </Trigger>
+        </Dataset>
+    </Core>
+</Project>
diff --git a/manufacturer/lattice/ecp5um/boards/darsena/labs.rvs b/manufacturer/lattice/ecp5um/boards/darsena/labs.rvs
new file mode 100644
index 0000000..67553e6
--- /dev/null
+++ b/manufacturer/lattice/ecp5um/boards/darsena/labs.rvs
@@ -0,0 +1,102 @@
+<Project ModBy="Analyzer" Name="C:/projects/lattice/privateisland/boards/darsena/labs.rvs" Date="2019-07-08">
+ <Core Name="lab_1_i2c">
+  <Setting>
+   <Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
+   <Event EventCnt="0" CntEnableRun="0"/>
+   <TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
+  </Setting>
+  <Dataset Name="Base">
+   <Trace>
+    <Sig Name="i2c_0/scl_i"/>
+    <Sig Name="i2c_0/scl_i_m1"/>
+    <Sig Name="i2c_0/scl_i_m2"/>
+    <Sig Name="i2c_0/scl_high"/>
+    <Sig Name="i2c_0/scl_low"/>
+    <Sig Name="i2c_0/sda_i"/>
+    <Sig Name="i2c_0/sda_i_m1"/>
+    <Sig Name="i2c_0/start"/>
+    <Sig Name="i2c_0/stop"/>
+    <Sig Name="i2c_0/run"/>
+    <Bus Name="i2c_0/bit_cnt" Radix="0">
+     <Sig Name="i2c_0/bit_cnt:0"/>
+     <Sig Name="i2c_0/bit_cnt:1"/>
+     <Sig Name="i2c_0/bit_cnt:2"/>
+     <Sig Name="i2c_0/bit_cnt:3"/>
+     <Sig Name="i2c_0/bit_cnt:4"/>
+    </Bus>
+    <Bus Name="i2c_0/dev_ad" Radix="0">
+     <Sig Name="i2c_0/dev_ad:0"/>
+     <Sig Name="i2c_0/dev_ad:1"/>
+     <Sig Name="i2c_0/dev_ad:2"/>
+     <Sig Name="i2c_0/dev_ad:3"/>
+     <Sig Name="i2c_0/dev_ad:4"/>
+     <Sig Name="i2c_0/dev_ad:5"/>
+     <Sig Name="i2c_0/dev_ad:6"/>
+    </Bus>
+    <Bus Name="i2c_0/addr" Radix="0">
+     <Sig Name="i2c_0/addr:0"/>
+     <Sig Name="i2c_0/addr:1"/>
+     <Sig Name="i2c_0/addr:2"/>
+     <Sig Name="i2c_0/addr:3"/>
+     <Sig Name="i2c_0/addr:4"/>
+     <Sig Name="i2c_0/addr:5"/>
+     <Sig Name="i2c_0/addr:6"/>
+     <Sig Name="i2c_0/addr:7"/>
+    </Bus>
+    <Bus Name="i2c_0/d" Radix="0">
+     <Sig Name="i2c_0/d:0"/>
+     <Sig Name="i2c_0/d:1"/>
+     <Sig Name="i2c_0/d:2"/>
+     <Sig Name="i2c_0/d:3"/>
+     <Sig Name="i2c_0/d:4"/>
+     <Sig Name="i2c_0/d:5"/>
+     <Sig Name="i2c_0/d:6"/>
+     <Sig Name="i2c_0/d:7"/>
+    </Bus>
+    <Sig Name="i2c_0/ack"/>
+    <Sig Name="i2c_0/rwn"/>
+    <Sig Name="i2c_0/cont_sel"/>
+    <Sig Name="i2c_0/cont_done"/>
+    <Bus Name="i2c_0/fifo_di" Radix="0">
+     <Sig Name="i2c_0/fifo_di:0"/>
+     <Sig Name="i2c_0/fifo_di:1"/>
+     <Sig Name="i2c_0/fifo_di:2"/>
+     <Sig Name="i2c_0/fifo_di:3"/>
+     <Sig Name="i2c_0/fifo_di:4"/>
+     <Sig Name="i2c_0/fifo_di:5"/>
+     <Sig Name="i2c_0/fifo_di:6"/>
+    </Bus>
+    <Sig Name="i2c_0/mem_we"/>
+    <Sig Name="i2c_0/cont_we"/>
+    <Bus Name="i2c_0/mem_do" Radix="0">
+     <Sig Name="i2c_0/mem_do:0"/>
+     <Sig Name="i2c_0/mem_do:1"/>
+     <Sig Name="i2c_0/mem_do:2"/>
+     <Sig Name="i2c_0/mem_do:3"/>
+     <Sig Name="i2c_0/mem_do:4"/>
+     <Sig Name="i2c_0/mem_do:5"/>
+     <Sig Name="i2c_0/mem_do:6"/>
+     <Sig Name="i2c_0/mem_do:7"/>
+    </Bus>
+    <Sig Name="i2c_0/fifo_re"/>
+    <Bus Name="i2c_0/i_di" Radix="0">
+     <Sig Name="i2c_0/i_di:0"/>
+     <Sig Name="i2c_0/i_di:1"/>
+     <Sig Name="i2c_0/i_di:2"/>
+     <Sig Name="i2c_0/i_di:3"/>
+     <Sig Name="i2c_0/i_di:4"/>
+     <Sig Name="i2c_0/i_di:5"/>
+     <Sig Name="i2c_0/i_di:6"/>
+     <Sig Name="i2c_0/i_di:7"/>
+    </Bus>
+    <Sig Name="i2c_0/sda_o"/>
+    <Sig Name="i2c_0/sda_oe"/>
+    <Sig Name="i2c_0/tx_fifo_empty"/>
+   </Trace>
+   <Trigger>
+    <TU Operator="0" Name="TU1" ID="1" Value="1" Radix="0"/>
+    <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
+   </Trigger>
+  </Dataset>
+ </Core>
+</Project>
-- 
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