From 6e969b02b4f6266bb9af926bfba6698468c74c28 Mon Sep 17 00:00:00 2001
From: mindchasers <privateisland@mindchasers.com>
Date: Mon, 16 Nov 2020 17:10:41 -0500
Subject: project: rename device to lattice to include specific manufacturers

---
 manufacturer/device/ecp5um/privateisland.ldf | 144 ---------------------------
 1 file changed, 144 deletions(-)
 delete mode 100644 manufacturer/device/ecp5um/privateisland.ldf

(limited to 'manufacturer/device/ecp5um/privateisland.ldf')

diff --git a/manufacturer/device/ecp5um/privateisland.ldf b/manufacturer/device/ecp5um/privateisland.ldf
deleted file mode 100644
index b167227..0000000
--- a/manufacturer/device/ecp5um/privateisland.ldf
+++ /dev/null
@@ -1,144 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="privateisland" device="LFE5UM-45F-8BG381C" default_implementation="impl1">
-    <Options>
-        <Option name="HDL type" value="Verilog"/>
-    </Options>
-    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="darsena">
-        <Options>
-            <Option name="HDL type" value="Verilog"/>
-            <Option name="include path" value="remote_files/include"/>
-            <Option name="lib" value="work"/>
-            <Option name="top" value="top"/>
-        </Options>
-        <Source name="../../../source/top.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/bin_to_ascii.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/cam.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/clk_gen.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/controller.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/definitions.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="../../../source/dpram.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/drop_fifo.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/drop2_fifo.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/ethernet_params.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="../../../source/fcs.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/half_fifo.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/i2c.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/interrupts.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/ipv4.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/link_timer.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/mac.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/mdio.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/mdio_cont.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/mdio_data_ti.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/metrics.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/pkt_filter.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/sgmii_params.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="../../../source/spi.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/switch.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/sync_fifo.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/sync4_fifo.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../source/sync2_fifo.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/pcs.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/pcs.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/refclk0/refclk0.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/sgmii0/sgmii0.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/sgmii0/sgmii0_softlogic.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/sgmii1/sgmii1.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/sgmii2/sgmii2.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/sgmii2/sgmii2_softlogic.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="clarity/pcs/sgmii3/sgmii3.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="boards/darsena/darsena_v02.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="boards/darsena/labs.rva" type="Reveal Analyzer Project File" type_short="RVA">
-            <Options/>
-        </Source>
-        <Source name="boards/darsena/labs.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-        <Source name="programming/local_background.xcf" type="Programming Project File" type_short="Programming" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="programming/local_jtag.xcf" type="Programming Project File" type_short="Programming">
-            <Options/>
-        </Source>
-        <Source name="programming/read_device_status.xcf" type="Programming Project File" type_short="Programming" excluded="TRUE">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="darsena" file="boards/darsena/darsena.sty"/>
-</BaliProject>
-- 
cgit v1.2.3-8-gadcc