From 3e6999c467908663d2539483de82057f587ffbb2 Mon Sep 17 00:00:00 2001
From: mindchasers <privateisland@mindchasers.com>
Date: Sun, 15 Nov 2020 23:42:42 -0500
Subject: ecp5um project: restructure so we can add more devices

---
 .../device/ecp5um/clarity/pcs/refclk0/refclk0.lpc  | 31 ++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc

(limited to 'manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc')

diff --git a/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc
new file mode 100644
index 0000000..1894b2d
--- /dev/null
+++ b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc
@@ -0,0 +1,31 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM-45F-8BG381C
+PartType=LFE5UM-45F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=EXTREF
+CoreRevision=1.1
+CoreStatus=Demo
+CoreType=LPM
+Date=03/06/2020
+ModuleName=refclk0
+ParameterFileVersion=1.0
+SourceFormat=verilog
+Time=20:20:44
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+Destination=Synplicity
+EDIF=1
+EXTREFDCBIAS=Disabled
+EXTREFTERMRES=50 ohms
+Expression=BusA(0 to 7)
+IO=0
+Order=Big Endian [MSB:LSB]
+VHDL=0
+Verilog=1
+[SYSTEMPNR]
+EXTREF=DCU0
-- 
cgit v1.2.3-8-gadcc