From 1c7478194daae4be777a21552295133a735082cb Mon Sep 17 00:00:00 2001 From: mindchasers Date: Sun, 27 Sep 2020 20:54:08 -0400 Subject: clarity: update SERDES/PCS block to be compatible with Diamond 3.11 --- clarity/pcs/sgmii0/sgmii0.fdc | 3 +- clarity/pcs/sgmii0/sgmii0.lpc | 12 ++--- clarity/pcs/sgmii0/sgmii0.v | 102 +++++++++++++++++++++--------------------- 3 files changed, 58 insertions(+), 59 deletions(-) (limited to 'clarity/pcs/sgmii0') diff --git a/clarity/pcs/sgmii0/sgmii0.fdc b/clarity/pcs/sgmii0/sgmii0.fdc index 292bc0f..6fbcac9 100644 --- a/clarity/pcs/sgmii0/sgmii0.fdc +++ b/clarity/pcs/sgmii0/sgmii0.fdc @@ -1,3 +1,2 @@ -###==== Start Generation +###==== Start Configuration -define_attribute {i:Lane0} {loc} {DCU0_CH0} diff --git a/clarity/pcs/sgmii0/sgmii0.lpc b/clarity/pcs/sgmii0/sgmii0.lpc index 0aea3d2..5c06b05 100644 --- a/clarity/pcs/sgmii0/sgmii0.lpc +++ b/clarity/pcs/sgmii0/sgmii0.lpc @@ -11,11 +11,11 @@ CoreName=PCS CoreRevision=8.2 CoreStatus=Demo CoreType=LPM -Date=02/08/2019 +Date=03/21/2020 ModuleName=sgmii0 ParameterFileVersion=1.0 SourceFormat=verilog -Time=18:42:05 +Time=21:48:39 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -25,8 +25,8 @@ VendorName=Lattice Semiconductor Corporation CDRLOLACTION=Full Recalibration CDRLOLRANGE=0 CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 +CDR_MULT=10X +CDR_REF_RATE=125.0000 CH_MODE=Rx and Tx Destination=Synplicity EDIF=1 @@ -44,7 +44,7 @@ PROTOCOL=GbE PWAIT_RX_RDY=3000 PWAIT_TX_RDY=3000 RCSRC=Disabled -REFCLK_RATE=50.0000 +REFCLK_RATE=125.0000 RSTSEQSEL=Disabled RX8B10B=Enabled RXCOMMAA=1010000011 @@ -80,7 +80,7 @@ TXFIFO_ENABLE=Enabled TXINVPOL=Invert TXLDR=Off TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X +TXPLLMULT=10X TX_DATA_WIDTH=8/10-Bit TX_FICLK_RATE=125.0000 TX_LINE_RATE=1.2500 diff --git a/clarity/pcs/sgmii0/sgmii0.v b/clarity/pcs/sgmii0/sgmii0.v index e2b5903..8cbf73e 100644 --- a/clarity/pcs/sgmii0/sgmii0.v +++ b/clarity/pcs/sgmii0/sgmii0.v @@ -1,12 +1,12 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 -// Netlist written on Sun Nov 18 17:44:07 2018 +// Verilog netlist produced by program ASBGen: Ports rev. 2.32, Attr. rev. 2.70 +// Netlist written on Sat Mar 21 21:49:34 2020 // // Verilog Description of module sgmii0 // `timescale 1ns/1ps module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, - tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + tx_pclk, txi_clk, tx_full_clk, txdata, tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, @@ -21,6 +21,7 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, input rxrefclk; output tx_pclk; input txi_clk; + output tx_full_clk; input [7:0]txdata; input [0:0]tx_k; input [0:0]xmit; @@ -66,18 +67,18 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, - n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n42, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, - n94, n95, n96, n97, n98, n99, n100, n101, _Z; + n94, n95, n96, n97, n98, n99, n100, _Z; DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(tx_pclk), .CH1_FF_RXI_CLK(1'b1), - .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_pclk), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_full_clk), .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), @@ -125,48 +126,48 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), - .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n47), .CH0_HDOUTN(hdoutn), - .CH1_HDOUTN(n48), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), + .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n46), .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n47), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n5), - .CH1_FF_RX_F_CLK(n49), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n50), - .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n51), .CH0_FF_TX_H_CLK(n8), - .CH1_FF_TX_H_CLK(n52), .CH0_FF_RX_PCLK(n9), .CH1_FF_RX_PCLK(n53), - .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n54), .CH0_FF_RX_D_0(rxdata[0]), - .CH1_FF_RX_D_0(n55), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n56), - .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n57), .CH0_FF_RX_D_3(rxdata[3]), - .CH1_FF_RX_D_3(n58), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n59), - .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n60), .CH0_FF_RX_D_6(rxdata[6]), - .CH1_FF_RX_D_6(n61), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n62), - .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n63), .CH0_FF_RX_D_9(rx_disp_err[0]), - .CH1_FF_RX_D_9(n64), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n65), - .CH0_FF_RX_D_11(n10), .CH1_FF_RX_D_11(n66), .CH0_FF_RX_D_12(n67), - .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), - .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), - .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), - .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), - .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), - .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), - .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), - .CH0_FF_RX_D_23(n11), .CH1_FF_RX_D_23(n89), .CH0_FFS_PCIE_DONE(n12), - .CH1_FFS_PCIE_DONE(n90), .CH0_FFS_PCIE_CON(n13), .CH1_FFS_PCIE_CON(n91), - .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n92), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), - .CH1_FFS_LS_SYNC_STATUS(n93), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), - .CH1_FFS_CC_UNDERRUN(n94), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n95), - .CH0_FFS_RXFBFIFO_ERROR(n14), .CH1_FFS_RXFBFIFO_ERROR(n96), .CH0_FFS_TXFBFIFO_ERROR(n15), - .CH1_FFS_TXFBFIFO_ERROR(n97), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n98), - .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n99), .CH0_FFS_SKP_DELETED(ctc_del_s), - .CH1_FFS_SKP_DELETED(n100), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .CH1_FF_RX_F_CLK(n48), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n49), + .CH0_FF_TX_F_CLK(tx_full_clk), .CH1_FF_TX_F_CLK(n50), .CH0_FF_TX_H_CLK(n7), + .CH1_FF_TX_H_CLK(n51), .CH0_FF_RX_PCLK(n8), .CH1_FF_RX_PCLK(n52), + .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n53), .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n54), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n55), + .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n56), .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n57), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n58), + .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n59), .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n60), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n61), + .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n62), .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n63), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n64), + .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n65), .CH0_FF_RX_D_12(n66), + .CH1_FF_RX_D_12(n67), .CH0_FF_RX_D_13(n68), .CH1_FF_RX_D_13(n69), + .CH0_FF_RX_D_14(n70), .CH1_FF_RX_D_14(n71), .CH0_FF_RX_D_15(n72), + .CH1_FF_RX_D_15(n73), .CH0_FF_RX_D_16(n74), .CH1_FF_RX_D_16(n75), + .CH0_FF_RX_D_17(n76), .CH1_FF_RX_D_17(n77), .CH0_FF_RX_D_18(n78), + .CH1_FF_RX_D_18(n79), .CH0_FF_RX_D_19(n80), .CH1_FF_RX_D_19(n81), + .CH0_FF_RX_D_20(n82), .CH1_FF_RX_D_20(n83), .CH0_FF_RX_D_21(n84), + .CH1_FF_RX_D_21(n85), .CH0_FF_RX_D_22(n86), .CH1_FF_RX_D_22(n87), + .CH0_FF_RX_D_23(n10), .CH1_FF_RX_D_23(n88), .CH0_FFS_PCIE_DONE(n11), + .CH1_FFS_PCIE_DONE(n89), .CH0_FFS_PCIE_CON(n12), .CH1_FFS_PCIE_CON(n90), + .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n91), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n92), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n93), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n94), + .CH0_FFS_RXFBFIFO_ERROR(n13), .CH1_FFS_RXFBFIFO_ERROR(n95), .CH0_FFS_TXFBFIFO_ERROR(n14), + .CH1_FFS_TXFBFIFO_ERROR(n96), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n97), + .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n98), .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n99), .CH0_LDR_RX2CORE(n100), .CH1_LDR_RX2CORE(_Z), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), - .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), - .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), - .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), - .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), - .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), - .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), - .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), - .D_REFCLKI(pll_refclki), .D_FFS_PLOL(pll_lol)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; + .D_SCAN_OUT_0(n15), .D_SCAN_OUT_1(n16), .D_SCAN_OUT_2(n17), .D_SCAN_OUT_3(n18), + .D_SCAN_OUT_4(n19), .D_SCAN_OUT_5(n20), .D_SCAN_OUT_6(n21), .D_SCAN_OUT_7(n22), + .D_COUT0(n23), .D_COUT1(n24), .D_COUT2(n25), .D_COUT3(n26), + .D_COUT4(n27), .D_COUT5(n28), .D_COUT6(n29), .D_COUT7(n30), + .D_COUT8(n31), .D_COUT9(n32), .D_COUT10(n33), .D_COUT11(n34), + .D_COUT12(n35), .D_COUT13(n36), .D_COUT14(n37), .D_COUT15(n38), + .D_COUT16(n39), .D_COUT17(n40), .D_COUT18(n41), .D_COUT19(n42), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n45)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; defparam DCU0_inst.D_MACROPDB = "0b1"; defparam DCU0_inst.D_IB_PWDNB = "0b1"; defparam DCU0_inst.D_XGE_MODE = "0b0"; @@ -314,7 +315,7 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, defparam DCU0_inst.D_CMUSETBIASI = "0b00"; defparam DCU0_inst.D_SETPLLRC = "0d1"; defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; - defparam DCU0_inst.D_REFCK_MODE = "0b100"; + defparam DCU0_inst.D_REFCK_MODE = "0b001"; defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; defparam DCU0_inst.D_RG_EN = "0b0"; @@ -361,7 +362,7 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n40 = 1'bz; assign n41 = 1'bz; assign n42 = 1'bz; - assign n43 = 1'bz; + assign n45 = 1'bz; assign n46 = 1'bz; assign n47 = 1'bz; assign n48 = 1'bz; @@ -417,19 +418,18 @@ module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, assign n98 = 1'bz; assign n99 = 1'bz; assign n100 = 1'bz; - assign n101 = 1'bz; assign _Z = 1'bz; sgmii0sll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), - .slo_plol()); + .slo_plol(pll_lol)); defparam sll_inst.PPROTOCOL = "GBE"; defparam sll_inst.PLOL_SETTING = 0; defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; defparam sll_inst.PPCIE_MAX_RATE = "2.5"; - defparam sll_inst.PDIFF_VAL_LOCK = 98; - defparam sll_inst.PDIFF_VAL_UNLOCK = 196; - defparam sll_inst.PPCLK_TC = 327680; + defparam sll_inst.PDIFF_VAL_LOCK = 20; + defparam sll_inst.PDIFF_VAL_UNLOCK = 40; + defparam sll_inst.PPCLK_TC = 65536; defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; defparam sll_inst.PPCLK_DIV11_TC = 0; -- cgit v1.2.3-8-gadcc