From 7b1b5e7eb712d41888398934834cae730e0aa5a0 Mon Sep 17 00:00:00 2001 From: Private Island Networks Inc Date: Sun, 21 Dec 2025 20:51:04 -0500 Subject: betsy: preliminary beta snapshot --- manufacturer/altera/cyclone10_lp/.gitignore | 12 + manufacturer/altera/cyclone10_lp/betsy.cof | 32 + manufacturer/altera/cyclone10_lp/betsy.jic | Bin 0 -> 16777447 bytes manufacturer/altera/cyclone10_lp/betsy.qpf | 31 + manufacturer/altera/cyclone10_lp/betsy.qsf | 742 +++ manufacturer/altera/cyclone10_lp/betsy.sdc | 84 + .../cyclone10_lp/betsy_assignment_defaults.qdf | 806 +++ .../altera/cyclone10_lp/brds/betsy/betsy.stp | 6345 ++++++++++++++++++++ .../altera/cyclone10_lp/ip/ddrio/ddrio.bsf | 114 + .../altera/cyclone10_lp/ip/ddrio/ddrio.ppf | 18 + .../altera/cyclone10_lp/ip/ddrio/ddrio.qip | 8 + manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v | 145 + .../altera/cyclone10_lp/ip/ddrio/ddrio_bb.v | 105 + .../altera/cyclone10_lp/ip/ddrio/ddrio_inst.v | 13 + manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf | 96 + manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf | 12 + manufacturer/altera/cyclone10_lp/ip/pll/pll.qip | 8 + manufacturer/altera/cyclone10_lp/ip/pll/pll.v | 348 ++ manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v | 232 + manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v | 7 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf | 65 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp | 25 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc | 26 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf | 11 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip | 10 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri.v | 103 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v | 74 + .../altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v | 6 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf | 79 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp | 27 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro.inc | 28 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf | 13 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro.qip | 10 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro.v | 115 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v | 84 + .../altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v | 8 + manufacturer/altera/cyclone10_lp/mle_ram_0.txt | 1024 ++++ manufacturer/altera/cyclone10_lp/mle_ram_1.txt | 1024 ++++ manufacturer/altera/cyclone10_lp/param_ram_0.txt | 1024 ++++ manufacturer/altera/cyclone10_lp/param_ram_1.txt | 1024 ++++ manufacturer/altera/cyclone10_lp/param_ram_2.txt | 1024 ++++ manufacturer/altera/cyclone10_lp/sim/.gitignore | 12 + .../altera/cyclone10_lp/sim/data/cont_mle_w.dat | 145 + .../altera/cyclone10_lp/sim/data/cont_query.dat | 145 + .../cyclone10_lp/sim/data/cont_query_fcs.dat | 72 + .../altera/cyclone10_lp/sim/data/etoe0.dat | 144 + .../altera/cyclone10_lp/sim/data/etoe1.dat | 144 + .../altera/cyclone10_lp/sim/data/etoe2.dat | 144 + manufacturer/altera/cyclone10_lp/sim/lin/README | 33 + manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf | 2329 +++++++ .../altera/cyclone10_lp/sim/lin/modelsim.ini | 2220 +++++++ manufacturer/altera/cyclone10_lp/sim/lin/wave.do | 307 + manufacturer/altera/cyclone10_lp/sim/sim.do | 4 + manufacturer/altera/cyclone10_lp/sim/src/tb.sv | 359 ++ manufacturer/altera/cyclone10_lp/sim/wav/wave.do | 294 + .../altera/cyclone10_lp/sim/wav/wave_cont.do | 367 ++ .../altera/cyclone10_lp/sim/wav/wave_cont_fcs.do | 325 + .../altera/cyclone10_lp/sim/wav/wave_etoe.do | 152 + .../altera/cyclone10_lp/sim/wav/wave_ml_engine.do | 206 + .../cyclone10_lp/sim/wav/wave_ml_engine_direct.do | 306 + manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf | 2342 ++++++++ .../altera/cyclone10_lp/sim/win/modelsim.ini | 2220 +++++++ manufacturer/altera/cyclone10_lp/src/betsy.v | 1916 ++++++ .../cyclone10_lp/src/betsy_passthrough_regs.v | 375 ++ manufacturer/altera/cyclone10_lp/zero.txt | 2048 +++++++ src/an.v | 122 - src/bin_to_ascii.v | 128 - src/cam.v | 48 +- src/clk_gen.v | 67 - src/cont_params.v | 61 + src/controller.v | 136 +- src/directives.v | 34 - src/dpram.v | 102 - src/dpram_inf.v | 84 + src/drop_fifo.v | 328 +- src/ethernet_params.v | 36 +- src/fcs.v | 155 +- src/half_fifo.v | 299 +- src/i2c.v | 391 -- src/interrupts.v | 77 - src/ipv4.v | 152 - src/ipv4_rx.v | 165 + src/ipv4_rx_c.v | 134 + src/ipv4_tx_c.v | 179 + src/ipv4_tx_mle.v | 175 + src/link_timer.v | 67 - src/mac.v | 973 --- src/mac_rgmii.v | 998 +++ src/mdio.v | 5 +- src/mdio_cont.v | 93 +- src/mdio_data_ti.v | 181 +- src/metrics.v | 102 - src/ml_engine.v | 563 ++ src/pkt_filter.v | 106 +- src/rgmii_params.v | 46 + src/sgmii_params.v | 55 - src/spi.v | 315 - src/switch.v | 656 +- src/sync_fifo.v | 13 +- src/udp_rx.v | 117 + src/udp_rx_c.v | 89 + 101 files changed, 35244 insertions(+), 3579 deletions(-) create mode 100644 manufacturer/altera/cyclone10_lp/.gitignore create mode 100644 manufacturer/altera/cyclone10_lp/betsy.cof create mode 100644 manufacturer/altera/cyclone10_lp/betsy.jic create mode 100644 manufacturer/altera/cyclone10_lp/betsy.qpf create mode 100644 manufacturer/altera/cyclone10_lp/betsy.qsf create mode 100644 manufacturer/altera/cyclone10_lp/betsy.sdc create mode 100644 manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf create mode 100644 manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp create mode 100644 manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf create mode 100644 manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf create mode 100644 manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip create mode 100644 manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf create mode 100644 manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf create mode 100644 manufacturer/altera/cyclone10_lp/ip/pll/pll.qip create mode 100644 manufacturer/altera/cyclone10_lp/ip/pll/pll.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v create mode 100644 manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v create mode 100644 manufacturer/altera/cyclone10_lp/mle_ram_0.txt create mode 100644 manufacturer/altera/cyclone10_lp/mle_ram_1.txt create mode 100644 manufacturer/altera/cyclone10_lp/param_ram_0.txt create mode 100644 manufacturer/altera/cyclone10_lp/param_ram_1.txt create mode 100644 manufacturer/altera/cyclone10_lp/param_ram_2.txt create mode 100644 manufacturer/altera/cyclone10_lp/sim/.gitignore create mode 100644 manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat create mode 100644 manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat create mode 100644 manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat create mode 100644 manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat create mode 100644 manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat create mode 100644 manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat create mode 100644 manufacturer/altera/cyclone10_lp/sim/lin/README create mode 100644 manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf create mode 100644 manufacturer/altera/cyclone10_lp/sim/lin/modelsim.ini create mode 100644 manufacturer/altera/cyclone10_lp/sim/lin/wave.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/sim.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/src/tb.sv create mode 100644 manufacturer/altera/cyclone10_lp/sim/wav/wave.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/wav/wave_cont.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/wav/wave_cont_fcs.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine_direct.do create mode 100644 manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf create mode 100644 manufacturer/altera/cyclone10_lp/sim/win/modelsim.ini create mode 100644 manufacturer/altera/cyclone10_lp/src/betsy.v create mode 100644 manufacturer/altera/cyclone10_lp/src/betsy_passthrough_regs.v create mode 100644 manufacturer/altera/cyclone10_lp/zero.txt delete mode 100644 src/an.v delete mode 100644 src/bin_to_ascii.v delete mode 100644 src/clk_gen.v create mode 100644 src/cont_params.v delete mode 100644 src/directives.v delete mode 100644 src/dpram.v create mode 100644 src/dpram_inf.v delete mode 100644 src/i2c.v delete mode 100644 src/interrupts.v delete mode 100644 src/ipv4.v create mode 100644 src/ipv4_rx.v create mode 100644 src/ipv4_rx_c.v create mode 100644 src/ipv4_tx_c.v create mode 100644 src/ipv4_tx_mle.v delete mode 100644 src/link_timer.v delete mode 100644 src/mac.v create mode 100644 src/mac_rgmii.v delete mode 100644 src/metrics.v create mode 100644 src/ml_engine.v create mode 100644 src/rgmii_params.v delete mode 100644 src/sgmii_params.v delete mode 100644 src/spi.v create mode 100644 src/udp_rx.v create mode 100644 src/udp_rx_c.v diff --git a/manufacturer/altera/cyclone10_lp/.gitignore b/manufacturer/altera/cyclone10_lp/.gitignore new file mode 100644 index 0000000..2e58f2c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/.gitignore @@ -0,0 +1,12 @@ +betsy_top.txt +db +greybox_tmp +incremental_db +simulation +output_* +*.bak +*.map +*.rpd +*.rpt +*.rpd +*.qws diff --git a/manufacturer/altera/cyclone10_lp/betsy.cof b/manufacturer/altera/cyclone10_lp/betsy.cof new file mode 100644 index 0000000..82b7d02 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.cof @@ -0,0 +1,32 @@ + + + MT25QL128 + 10CL025Y + output_file.jic + 1 + 1 + 7 + + Page_0 + 1 + + C:/Projects/PrivateIsland/pi-betsy/manufacturer/intel/cyclone10_lp/output_betsy/betsy.sof + + + 10 + 0 + 0 + 0 + 1 + + 1 + + + 1 + 2 + 0 + -1 + -1 + 1 + + \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy.jic b/manufacturer/altera/cyclone10_lp/betsy.jic new file mode 100644 index 0000000..501f0f1 Binary files /dev/null and b/manufacturer/altera/cyclone10_lp/betsy.jic differ diff --git a/manufacturer/altera/cyclone10_lp/betsy.qpf b/manufacturer/altera/cyclone10_lp/betsy.qpf new file mode 100644 index 0000000..c6aaaba --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 23.1std.0 Build 991 11/28/2023 Patches 0.02std SC Lite Edition +# Date created = 13:02:56 May 09, 2024 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "23.1" +DATE = "13:02:56 May 09, 2024" + +# Revisions + +PROJECT_REVISION = "betsy" diff --git a/manufacturer/altera/cyclone10_lp/betsy.qsf b/manufacturer/altera/cyclone10_lp/betsy.qsf new file mode 100644 index 0000000..2d4da4c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.qsf @@ -0,0 +1,742 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 00:31:06 February 23, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# betsy_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name DEVICE 10CL025YU256I7G +set_global_assignment -name TOP_LEVEL_ENTITY betsy +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:31:06 FEBRUARY 23, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Standard Edition" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE MT25QL128 +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_betsy + + + +# Bank 1 Configuration, Sheet 6 +set_location_assignment PIN_E1 -to flash_dqs +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_dqs +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_dqs + +set_location_assignment PIN_B1 -to flash_d[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[4] + +set_location_assignment PIN_C1 -to flash_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[0] + +set_location_assignment PIN_D2 -to flash_seln +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_seln + +set_location_assignment PIN_G1 -to rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rstn + +set_location_assignment PIN_H1 -to flash_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_clk + +set_location_assignment PIN_H2 -to flash_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[1] + +# JTAG is defined in bank 1. Can this be supported in user mode? + + +# Bank 2 RGMII 0, Sheet 3 +set_location_assignment PIN_M1 -to phy0_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_clk + +set_location_assignment PIN_J2 -to phy0_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_ctl + +set_location_assignment PIN_J1 -to phy0_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_ctl + +set_location_assignment PIN_K2 -to phy0_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[2] + +set_location_assignment PIN_K1 -to phy0_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[3] + +set_location_assignment PIN_L2 -to phy0_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[0] + +set_location_assignment PIN_L1 -to phy0_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[1] + +# L3 + +set_location_assignment PIN_N2 -to phy0_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_intn + +set_location_assignment PIN_N1 -to phy0_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rstn + +# K5 +# L4 + +set_location_assignment PIN_R1 -to phy0_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_gpio[0] + +# P2 + +set_location_assignment PIN_P1 -to phy0_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_gpio[1] + + +# Bank 3 RGMII 0, Sheet 3 +set_location_assignment PIN_T8 -to phy0_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_clk + +# N3 +# P3 + +set_location_assignment PIN_R3 -to phy0_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[1] + +set_location_assignment PIN_T3 -to phy0_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[0] + +set_location_assignment PIN_T2 -to phy0_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_clk + +set_location_assignment PIN_R4 -to phy0_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[3] + +set_location_assignment PIN_T4 -to phy0_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[2] + +# N5 +# N6 +# M6 +# P6 +# M7 +# R5 +# T5 +# R6 + +set_location_assignment PIN_T6 -to phy0_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_mdio + +# L7 +# R7 + +set_location_assignment PIN_T7 -to phy0_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_mdc + +# L8 +# M8 +# N8 +# P8 + +# Bank 4, RGMII 1, Sheet 4 +set_location_assignment PIN_T9 -to phy1_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_clk + +set_location_assignment PIN_T10 -to phy1_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[3] + +set_location_assignment PIN_T11 -to phy1_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[2] + +set_location_assignment PIN_T12 -to phy1_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[1] + +set_location_assignment PIN_P9 -to phy1_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_gpio[0] + +set_location_assignment PIN_R13 -to phy1_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_ctl + +set_location_assignment PIN_T13 -to phy1_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[0] + +set_location_assignment PIN_T14 -to phy1_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_ctl + +set_location_assignment PIN_T15 -to phy1_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_clk + +set_location_assignment PIN_P14 -to phy1_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rstn + + +# Bank 5, RGMII 1, Sheet 4 +set_location_assignment PIN_P15 -to phy1_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_clk + +set_location_assignment PIN_P16 -to phy1_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[1] + +set_location_assignment PIN_R16 -to phy1_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[0] + +set_location_assignment PIN_N16 -to phy1_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[3] + +set_location_assignment PIN_N15 -to phy1_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[2] + +set_location_assignment PIN_L16 -to phy1_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_mdio + +set_location_assignment PIN_L15 -to phy1_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_intn + +set_location_assignment PIN_K16 -to phy1_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_mdc + +set_location_assignment PIN_K15 -to phy1_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_gpio[1] + +set_location_assignment PIN_J16 -to phy2_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_mdio + +set_location_assignment PIN_J15 -to phy2_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_mdc + + +# Bank 6, RGMII 2, Sheet 5 +set_location_assignment PIN_E16 -to phy2_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_clk + +set_location_assignment PIN_G16 -to phy2_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[2] + +set_location_assignment PIN_G15 -to phy2_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[3] + +set_location_assignment PIN_F16 -to phy2_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_ctl + +set_location_assignment PIN_F15 -to phy2_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[1] + +set_location_assignment PIN_B16 -to phy2_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_gpio[1] + +set_location_assignment PIN_D16 -to phy2_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[0] + +set_location_assignment PIN_D15 -to phy2_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_intn + +set_location_assignment PIN_C16 -to phy2_gpio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_gpio + +# Bank 7, RGMII 2, Sheet 5 +set_location_assignment PIN_A13 -to phy2_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[1] + +set_location_assignment PIN_A14 -to phy2_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_ctl + +set_location_assignment PIN_B14 -to phy2_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rstn + +set_location_assignment PIN_A12 -to phy2_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[0] + +set_location_assignment PIN_A11 -to phy2_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[2] + +set_location_assignment PIN_A15 -to phy2_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_clk + +set_location_assignment PIN_A10 -to phy2_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[3] + +# Bank 8 + +set_location_assignment PIN_A7 -to fpga_led[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[2] + +set_location_assignment PIN_A6 -to fpga_led[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[1] + +set_location_assignment PIN_A5 -to fpga_led[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[0] + +set_location_assignment PIN_A4 -to flash_d[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[7] + +set_location_assignment PIN_B4 -to flash_d[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[5] + +set_location_assignment PIN_A2 -to flash_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[2] + +set_location_assignment PIN_A3 -to flash_d[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[6] + +set_location_assignment PIN_B3 -to flash_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[3] + + + + + + +set_location_assignment PIN_A8 -to clk_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SDC_FILE betsy.sdc +set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name VERILOG_FILE src/betsy.v +set_global_assignment -name VERILOG_FILE ../../../src/cam.v +set_global_assignment -name VERILOG_FILE ../../../src/controller.v +set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v +set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v +set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v +set_global_assignment -name VERILOG_FILE ../../../src/fcs.v +set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v +set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v +set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v +set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v +set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v +set_global_assignment -name VERILOG_FILE ../../../src/rm.v +set_global_assignment -name VERILOG_FILE ../../../src/switch.v +set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v +set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip +set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip +set_global_assignment -name QIP_FILE ip/pll/pll.qip +set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip +set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv + +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id tst_controller +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:pll_0|c0" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "controller:controller_0|msg_addr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "controller:controller_0|msg_addr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "controller:controller_0|msg_addr[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "controller:controller_0|msg_addr[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "controller:controller_0|msg_addr[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "controller:controller_0|msg_addr[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "controller:controller_0|msg_addr[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "controller:controller_0|msg_addr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "controller:controller_0|msg_addr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "controller:controller_0|msg_addr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "controller:controller_0|msg_addr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "controller:controller_0|msg_addr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "controller:controller_0|msg_addr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "controller:controller_0|msg_addr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "controller:controller_0|msg_addr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "controller:controller_0|msg_addr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "controller:controller_0|msg_addr_ro" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "controller:controller_0|msg_addr_valid" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "controller:controller_0|msg_data[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "controller:controller_0|msg_data[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "controller:controller_0|msg_data[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "controller:controller_0|msg_data[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "controller:controller_0|msg_data[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "controller:controller_0|msg_data[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "controller:controller_0|msg_data[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "controller:controller_0|msg_data[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "controller:controller_0|msg_data[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "controller:controller_0|msg_data[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "controller:controller_0|msg_data[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "controller:controller_0|msg_data[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "controller:controller_0|msg_data[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "controller:controller_0|msg_data[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "controller:controller_0|msg_data[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "controller:controller_0|msg_data[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "controller:controller_0|msg_data[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "controller:controller_0|msg_data[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "controller:controller_0|msg_data[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "controller:controller_0|msg_data[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "controller:controller_0|msg_data[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "controller:controller_0|msg_data[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "controller:controller_0|msg_data[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "controller:controller_0|msg_data[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "controller:controller_0|msg_data[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "controller:controller_0|msg_data[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "controller:controller_0|msg_data[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "controller:controller_0|msg_data[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "controller:controller_0|msg_data[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "controller:controller_0|msg_data[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "controller:controller_0|msg_data[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "controller:controller_0|msg_data[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "controller:controller_0|msg_error" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "controller:controller_0|msg_response[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "controller:controller_0|msg_response[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "controller:controller_0|msg_response[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "controller:controller_0|msg_response[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "controller:controller_0|msg_response[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "controller:controller_0|msg_response[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "controller:controller_0|msg_response[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "controller:controller_0|msg_response[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "controller:controller_0|msg_response[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "controller:controller_0|msg_response[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "controller:controller_0|msg_response[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "controller:controller_0|msg_response[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "controller:controller_0|msg_response[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "controller:controller_0|msg_response[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "controller:controller_0|msg_response[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "controller:controller_0|msg_response[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "controller:controller_0|msg_response[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "controller:controller_0|msg_response[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "controller:controller_0|msg_response[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "controller:controller_0|msg_response[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "controller:controller_0|msg_response[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "controller:controller_0|msg_response[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "controller:controller_0|msg_response[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "controller:controller_0|msg_response[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "controller:controller_0|msg_response[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "controller:controller_0|msg_response[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "controller:controller_0|msg_response[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "controller:controller_0|msg_response[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "controller:controller_0|msg_response[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "controller:controller_0|msg_response[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "controller:controller_0|msg_response[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "controller:controller_0|msg_response[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "controller:controller_0|msg_token[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "controller:controller_0|msg_token[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "controller:controller_0|msg_token[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "controller:controller_0|msg_token[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "controller:controller_0|msg_token[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "controller:controller_0|msg_token[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "controller:controller_0|msg_token[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "controller:controller_0|msg_token[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "controller:controller_0|msg_type[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "controller:controller_0|msg_type[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "controller:controller_0|msg_type[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "controller:controller_0|msg_type[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "controller:controller_0|msg_type[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "controller:controller_0|msg_type[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "controller:controller_0|msg_type[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "controller:controller_0|msg_type[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "controller:controller_0|rx_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "controller:controller_0|rx_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "controller:controller_0|rx_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "controller:controller_0|rx_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "controller:controller_0|rx_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "controller:controller_0|rx_fifo_int" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "controller:controller_0|rx_fifo_int_acked" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "controller:controller_0|rx_fifo_int_m1" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "controller:controller_0|rx_fifo_int_m2" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "controller:controller_0|rx_msg_captured" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "controller:controller_0|rx_msg_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "controller:controller_0|rx_msg_cnt[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "controller:controller_0|rx_msg_cnt[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "controller:controller_0|rx_msg_cnt[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "controller:controller_0|rx_msg_cnt[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "controller:controller_0|rx_msg_cnt[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "controller:controller_0|rx_msg_cnt[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "controller:controller_0|rx_msg_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "controller:controller_0|rx_msg_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "controller:controller_0|rx_msg_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "controller:controller_0|rx_msg_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "controller:controller_0|rx_msg_cnt[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "controller:controller_0|rx_msg_cnt[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "controller:controller_0|rx_msg_cnt[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "controller:controller_0|rx_msg_cnt[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "controller:controller_0|rx_msg_cnt[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "controller:controller_0|rx_rd_active" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "controller:controller_0|rx_rd_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "controller:controller_0|rx_rd_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "controller:controller_0|rx_rd_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "controller:controller_0|rx_rd_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "controller:controller_0|rx_rd_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "controller:controller_0|rx_rd_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "controller:controller_0|rx_rd_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "controller:controller_0|rx_rd_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "controller:controller_0|rx_rd_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "controller:controller_0|rx_rd_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "controller:controller_0|rx_rd_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "controller:controller_0|rx_wr_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "controller:controller_0|rx_wr_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "controller:controller_0|rx_wr_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "controller:controller_0|rx_wr_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "controller:controller_0|rx_wr_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "controller:controller_0|rx_wr_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "controller:controller_0|rx_wr_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "controller:controller_0|rx_wr_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "controller:controller_0|rx_wr_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "controller:controller_0|rx_wr_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "controller:controller_0|rx_wr_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "controller:controller_0|msg_addr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "controller:controller_0|msg_addr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "controller:controller_0|msg_addr[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "controller:controller_0|msg_addr[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "controller:controller_0|msg_addr[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "controller:controller_0|msg_addr[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "controller:controller_0|msg_addr[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "controller:controller_0|msg_addr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "controller:controller_0|msg_addr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "controller:controller_0|msg_addr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "controller:controller_0|msg_addr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "controller:controller_0|msg_addr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "controller:controller_0|msg_addr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "controller:controller_0|msg_addr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "controller:controller_0|msg_addr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "controller:controller_0|msg_addr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "controller:controller_0|msg_addr_ro" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "controller:controller_0|msg_addr_valid" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "controller:controller_0|msg_data[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "controller:controller_0|msg_data[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "controller:controller_0|msg_data[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "controller:controller_0|msg_data[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "controller:controller_0|msg_data[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "controller:controller_0|msg_data[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "controller:controller_0|msg_data[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "controller:controller_0|msg_data[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "controller:controller_0|msg_data[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "controller:controller_0|msg_data[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "controller:controller_0|msg_data[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "controller:controller_0|msg_data[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "controller:controller_0|msg_data[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "controller:controller_0|msg_data[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "controller:controller_0|msg_data[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "controller:controller_0|msg_data[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "controller:controller_0|msg_data[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "controller:controller_0|msg_data[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "controller:controller_0|msg_data[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "controller:controller_0|msg_data[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "controller:controller_0|msg_data[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "controller:controller_0|msg_data[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "controller:controller_0|msg_data[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "controller:controller_0|msg_data[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "controller:controller_0|msg_data[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "controller:controller_0|msg_data[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "controller:controller_0|msg_data[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "controller:controller_0|msg_data[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "controller:controller_0|msg_data[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "controller:controller_0|msg_data[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "controller:controller_0|msg_data[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "controller:controller_0|msg_data[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "controller:controller_0|msg_error" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "controller:controller_0|msg_response[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "controller:controller_0|msg_response[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "controller:controller_0|msg_response[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "controller:controller_0|msg_response[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "controller:controller_0|msg_response[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "controller:controller_0|msg_response[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "controller:controller_0|msg_response[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "controller:controller_0|msg_response[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "controller:controller_0|msg_response[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "controller:controller_0|msg_response[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "controller:controller_0|msg_response[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "controller:controller_0|msg_response[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "controller:controller_0|msg_response[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "controller:controller_0|msg_response[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "controller:controller_0|msg_response[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "controller:controller_0|msg_response[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "controller:controller_0|msg_response[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "controller:controller_0|msg_response[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "controller:controller_0|msg_response[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "controller:controller_0|msg_response[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "controller:controller_0|msg_response[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "controller:controller_0|msg_response[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "controller:controller_0|msg_response[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "controller:controller_0|msg_response[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "controller:controller_0|msg_response[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "controller:controller_0|msg_response[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "controller:controller_0|msg_response[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "controller:controller_0|msg_response[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "controller:controller_0|msg_response[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "controller:controller_0|msg_response[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "controller:controller_0|msg_response[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "controller:controller_0|msg_response[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "controller:controller_0|msg_token[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "controller:controller_0|msg_token[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "controller:controller_0|msg_token[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "controller:controller_0|msg_token[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "controller:controller_0|msg_token[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "controller:controller_0|msg_token[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "controller:controller_0|msg_token[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "controller:controller_0|msg_token[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "controller:controller_0|msg_type[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "controller:controller_0|msg_type[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "controller:controller_0|msg_type[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "controller:controller_0|msg_type[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "controller:controller_0|msg_type[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "controller:controller_0|msg_type[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "controller:controller_0|msg_type[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "controller:controller_0|msg_type[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "controller:controller_0|rx_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "controller:controller_0|rx_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "controller:controller_0|rx_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "controller:controller_0|rx_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "controller:controller_0|rx_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "controller:controller_0|rx_fifo_int" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "controller:controller_0|rx_fifo_int_acked" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "controller:controller_0|rx_fifo_int_m1" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "controller:controller_0|rx_fifo_int_m2" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "controller:controller_0|rx_msg_captured" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "controller:controller_0|rx_msg_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "controller:controller_0|rx_msg_cnt[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "controller:controller_0|rx_msg_cnt[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "controller:controller_0|rx_msg_cnt[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "controller:controller_0|rx_msg_cnt[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "controller:controller_0|rx_msg_cnt[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "controller:controller_0|rx_msg_cnt[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "controller:controller_0|rx_msg_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "controller:controller_0|rx_msg_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "controller:controller_0|rx_msg_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "controller:controller_0|rx_msg_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "controller:controller_0|rx_msg_cnt[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "controller:controller_0|rx_msg_cnt[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "controller:controller_0|rx_msg_cnt[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "controller:controller_0|rx_msg_cnt[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "controller:controller_0|rx_msg_cnt[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "controller:controller_0|rx_rd_active" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "controller:controller_0|rx_rd_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "controller:controller_0|rx_rd_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "controller:controller_0|rx_rd_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "controller:controller_0|rx_rd_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "controller:controller_0|rx_rd_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "controller:controller_0|rx_rd_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "controller:controller_0|rx_rd_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "controller:controller_0|rx_rd_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "controller:controller_0|rx_rd_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "controller:controller_0|rx_rd_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "controller:controller_0|rx_rd_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "controller:controller_0|rx_wr_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "controller:controller_0|rx_wr_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "controller:controller_0|rx_wr_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "controller:controller_0|rx_wr_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "controller:controller_0|rx_wr_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "controller:controller_0|rx_wr_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "controller:controller_0|rx_wr_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "controller:controller_0|rx_wr_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "controller:controller_0|rx_wr_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "controller:controller_0|rx_wr_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "controller:controller_0|rx_wr_ptr[9]" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=148" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=148" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=148" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334538" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=466" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=256" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to tst_controller|vcc -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id tst_controller +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/betsy_auto_stripped.stp \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy.sdc b/manufacturer/altera/cyclone10_lp/betsy.sdc new file mode 100644 index 0000000..9d58e0c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.sdc @@ -0,0 +1,84 @@ +create_clock -name clk -period 40.0 [get_ports clk_i]; + +create_clock -name phy0_rx_clk_v -period 8.0; # virtual clock for input constraint timing +create_clock -name phy0_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy0_rx_clk]; + +create_clock -name phy1_rx_clk_v -period 8.0; # virtual clock for input constraint timing +create_clock -name phy1_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy1_rx_clk]; + +create_clock -name phy2_rx_clk_v -period 8.0; # virtual clock for input constraint timi +create_clock -name phy2_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy2_rx_clk]; + + +create_clock -name phy0_tx_clk -period 8.0 [get_ports phy0_tx_clk]; +create_clock -name phy0_tx_clk_v -period 8.0; # virtual clock for input constraint timing + +create_clock -name phy1_tx_clk -period 8.0 [get_ports phy1_tx_clk]; +create_clock -name phy1_tx_clk_v -period 8.0; # virtual clock for input constraint timing + +create_clock -name phy2_tx_clk -period 8.0 [get_ports phy2_tx_clk]; +create_clock -name phy2_tx_clk_v -period 8.0; # virtual clock for input constraint timing + + +create_clock -name phy0_clk -period 8.0 [get_ports phy0_clk]; + +derive_pll_clocks -create_base_clocks -use_net_name + +create_clock -name flash_dqs -period 10.0 [get_ports flash_dqs]; + +# PHY0 Input Clock +set_input_delay -min -0.8 -clock { phy0_rx_clk_v } [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { phy0_rx_clk_v } -clock_fall [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay + +set_input_delay -max 0.8 -clock { phy0_rx_clk_v } [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { phy0_rx_clk_v } -clock_fall [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay + +# PHY1 Input Clock +set_input_delay -min -0.8 -clock { phy1_rx_clk_v } [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { phy1_rx_clk_v } -clock_fall [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay; + +set_input_delay -max 0.8 -clock { phy1_rx_clk_v } [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { phy1_rx_clk_v } -clock_fall [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay; + +# phy2 Input Clock +set_input_delay -min -0.8 -clock { phy2_rx_clk_v } [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { phy2_rx_clk_v } -clock_fall [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay; + +set_input_delay -max 0.8 -clock { phy2_rx_clk_v } [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { phy2_rx_clk_v } -clock_fall [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay; + + +# Set false paths to remove irrelevant setup and hold analysis +set_false_path -fall_from [get_clocks phy0_rx_clk_v] -rise_to [get_clocks {phy0_rx_clk}] -setup +set_false_path -rise_from [get_clocks phy0_rx_clk_v] -fall_to [get_clocks {phy0_rx_clk}] -setup +set_false_path -fall_from [get_clocks phy0_rx_clk_v] -fall_to [get_clocks {phy0_rx_clk}] -hold +set_false_path -rise_from [get_clocks phy0_rx_clk_v] -rise_to [get_clocks {phy0_rx_clk}] -hold + +set_false_path -fall_from [get_clocks phy1_rx_clk_v] -rise_to [get_clocks {phy1_rx_clk}] -setup +set_false_path -rise_from [get_clocks phy1_rx_clk_v] -fall_to [get_clocks {phy1_rx_clk}] -setup +set_false_path -fall_from [get_clocks phy1_rx_clk_v] -fall_to [get_clocks {phy1_rx_clk}] -hold +set_false_path -rise_from [get_clocks phy1_rx_clk_v] -rise_to [get_clocks {phy1_rx_clk}] -hold + + +set_false_path -fall_from [get_clocks phy2_rx_clk_v] -rise_to [get_clocks {phy2_rx_clk}] -setup +set_false_path -rise_from [get_clocks phy2_rx_clk_v] -fall_to [get_clocks {phy2_rx_clk}] -setup +set_false_path -fall_from [get_clocks phy2_rx_clk_v] -fall_to [get_clocks {phy2_rx_clk}] -hold +set_false_path -rise_from [get_clocks phy2_rx_clk_v] -rise_to [get_clocks {phy2_rx_clk}] -hold + +set_output_delay -max 0.5 -clock { phy0_tx_clk } [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay +set_output_delay -max 0.5 -clock { phy0_tx_clk } -clock_fall [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { phy0_tx_clk } [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { phy0_tx_clk } -clock_fall [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay + +set_output_delay -max 0.5 -clock { phy1_tx_clk } [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] +set_output_delay -max 0.5 -clock { phy1_tx_clk } -clock_fall [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { phy1_tx_clk } [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { phy1_tx_clk } -clock_fall [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay + +set_output_delay -max 0.5 -clock { phy2_tx_clk } [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] +set_output_delay -max 0.5 -clock { phy2_tx_clk } -clock_fall [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { phy2_tx_clk } [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { phy2_tx_clk } -clock_fall [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf b/manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf new file mode 100644 index 0000000..b0bacd2 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf @@ -0,0 +1,806 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2022 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +# Date created = 12:01:56 May 07, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp b/manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp new file mode 100644 index 0000000..f87d148 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp @@ -0,0 +1,6345 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'rx1_ctl_m2[0]' == high && 'rx1_ctl_m2[1]' == high + + + + + + 1111111111111111111111111111111111111111111111111111111111111 + 1111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + 10110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011101101011010110101100000000001011000010111011101110111011101110110101101011010110000000000101100001011101110111011101110111011010110101101011000000000010110000101110111011101110111011 + 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'pll:pll_0|locked' == high + + + + + + 11111111111111111111111111111111111111 + 11111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + 11100111100101110011000010000011111111111001111001011100110000100000011111110110011110010111001100001000000101111101100111100101110011000010000011011111011001111001011100110000100000111111111110111110010111001100001000001111111111101111100101110011000010000001111111011011111001011100110000100000010111110110111110010111001100001000001101111101101111100101110011000010000011111111111001111001011000110010100000111111111110011110010110001100101000000111111101100111100101100011001010000001011111011001111001011000110010100000110111110110011110010110001100101000001111111111101111100101100011001010000011111111111011111001011000110010100000011111110110111110010110001100101000000101111101101111100101100011001010000011011111011011111001011000110010100000111111111110011110010111001100101000001111111111100111100101110011001010000001111111011001111001011100110010100000010111110110011110010111001100101000001101111101100111100101110011001010000011111111111011111001011100110010100000111111111110111110010111001100101000000111111101101111100101110011001010000001011111011011111001011100110010100000110111110110111110010111001100101000001111111111100111100101100011000110000011111111111001111001011000110001100000011111110110011110010110001100011000000101111101100111100101100011000110000011011111011001111001011000110001100000111111111110111110010110001100011000001111111111101111100101100011000110000001111111011011111001011000110001100000010111110110111110010110001100011000001101111101101111100101100011000110000011111111111001111001011100110001100000111111111110011110010111001100011000000111111101100111100101110011000110000001011111011001111001011100110001100000110111110110011110010111001100011000001111111111101111100101110011000110000011111111111011111001011100110001100000011111110110111110010111001100011000000101111101101111100101110011000110000011011111011011111001011100110001100000111111111110011110010110001100111000001111111111100111100101100011001110000001111111011001111001011000110011100000010111110110011110010110001100111000001101111101100111100101100011001110000011111111111011111001011000110011100000111111111110111110010110001100111000000111111101101111100101100011001110000001011111011011111001011000110011100000110111110110111110010110001100111000001111111111100111100101110011001110000011111111111001111001011100110011100000011111110110011110010111001100111000000101111101100111100101110011001110000011011111011001111001011100110011100000111111111110111110010111001100111000001111111111101111100101110011001110000001111111011011111001011100110011100000010111110110111110010111001100111000001101111101101111100101110011001110000011111111111001111001011000110000010000111111111110011110010110001100000100000111111101100111100101100011000001000001011111011001111001011000110000010000110111110110011110010110001100000100001111111111101111100101100011000001000011111111111011111001011000110000010000011111110110111110010110001100000100000101111101101111100101100011000001000011011111011011111001011000110000010000111111111110011110010111001100000100001111111111100111100101110011000001000001111111011001111001011100110000010000010111110110011110010111001100000100001101111101100111100101110011000001000011111111111011111001011100110000010000111111111110111110010111001100000100000111111101101111100101110011000001000001011111011011111001011100110000010000110111110110111110010111001100000100001111111111100111100101100011001001000011111111111001111001011000110010010000011111110110011110010110001100100100000101111101100111100101100011001001000011011111011001111001011000110010010000111111111110111110010110001100100100001111111111101111100101100011001001000001111111011011111001011000110010010000010111110110111110010110001100100100001101111101101111100101100011001001000011111111111001111001011100110010010000111111111110011110010111001100100100000111111101100111100101110011001001000001011111011001111001011100110010010000110111110110011110010111001100100100001111111111101111100101110011001001000011111111111011111001011100110010010000011111110110111110010111001100100100000101111101101111100101110011001001000011011111011011111001011100110010010000111111111110011110010110001100010100001111111111100111100101100011000101000001111111011001111001011000110001010000010111110110011110010110001100010100001101111101100111100101100011000101000011111111111011111001011000110001010000111111111110111110010110001100010100000111111101101111100101100011000101000001011111011011111001011000110001010000110111110110111110010110001100010100001111111111100111100101110011000101000011111111111001111001011100110001010000011111110110011110010111001100010100000101111101100111100101110011000101000011011111011001111001011100110001010000111111111110111110010111001100010100001111111111101111100101110011000101000001111111011011111001011100110001010000010111110110111110010111001100010100001101111101101111100101110011000101000011111111111001111001011000110011010000111111111110011110010110001100110100000111111101100111100101100011001101000001011111011001111001011000110011010000110111110110011110010110001100110100001111111111101111100101100011001101000011111111111011111001011000110011010000011111110110111110010110001100110100000101111101101111100101100011001101000011011111011011111001011000110011010000111111111110011110010111001100110100001111111111100111100101110011001101000001111111011001111001011100110011010000010111110110011110010111001100110100001101111101100111100101110011001101000011111111111011111001011100110011010000111111111110111110010111001100110100000111111101101111100101110011001101000001011111011011111001011100110011010000110111110110111110010111001100110100001111111111100111100101100011000011000011111111111001111001011000110000110000011111110110011110010110001100001100000101111101100111100101100011000011000011011111011001111001011000110000110000111111111110111110010110001100001100001111111111101111100101100011000011000001111111011011111001011000110000110000010111110110111110010110001100001100001101111101101111100101100011000011000011111111111001111001011100110000110000111111111110011110010111001100001100000111111101100111100101110011000011000001011111011001111001011100110000110000110111110110011110010111001100001100001111111111101111100101110011000011000011111111111011111001011100110000110000011111110110111110010111001100001100000101111101101111100101110011000011000011011111011011111001011100110000110000111111111110011110010110001100101100001111111111100111100101100011001011000001111111011001111001011000110010110000010111110110011110010110001100101100001101111101100111100101100011001011000011111111111011111001011000110010110000111111111110111110010110001100101100000111111101101111100101100011001011000001011111011011111001011000110010110000110111110110111110010110001100101100001111111111100111100101110011001011000011111111111001111001011100110010110000011111110110011110010111001100101100000101111101100111100101110011001011000011011111011001111001011100110010110000111111111110111110010111001100101100001111111111101111100101110011001011000001111111011011111001011100110010110000010111110110111110010111001100101100001101111101101111100101110011001011000011111111111001111001011000110001110000111111111110011110010110001100011100000111111101100111100101100011000111000001011111011001111001011000110001110000110111110110011110010110001100011100001111111111101111100101100011000111000011111111111011111001011000110001110000011111110110111110010110001100011100000101111101101111100101100011000111000011011111011011111001011000110001110000111111111110011110010111001100011100001111111111100111100101110011000111000001111111011001111001011100110001110000010111110110011110010111001100011100001101111101100111100101110011000111000011111111111011111001011100110001110000111111111110111110010111001100011100000111111101101111100101110011000111000001011111011011111001011100110001110000110111110110111110010111001100011100001111111111100111100101100011001111000011111111111001111001011000110011110000011111110110011110010110001100111100000101111101100111100101100011001111000011011111011001111001011000110011110000111111111110111110010110001100111100001111111111101111100101100011001111000001111111011011111001011000110011110000010111110110111110010110001100111100001101111101101111100101100011001111000011111111111001111001011100110011110000111111111110011110010111001100111100000111111101100111100101110011001111000001011111011001111001011100110011110000110111110110011110010111001100111100001111111111101111100101110011001111000011111111111011111001011100110011110000011111110110111110010111001100111100000101111101101111100101110011001111000011011111011011111001011100110011110000111111111110011110010110001100000010001111111111100111100101100011000000100001111111011001111001011000110000001000010111110110011110010110001100000010001101111101100111100101100011000000100011111111111011111001011000110000001000111111111110111110010110001100000010000111111101101111100101100011000000100001011111011011111001011000110000001000110111110110111110010110001100000010001111111111100111100101110011000000100011111111111001111001011100110000001000011111110110011110010111001100000010000101111101100111100101110011000000100011011111011001111001011100110000001000111111111110111110010111001100000010001111111111101111100101110011000000100001111111011011111001011100110000001000010111110110111110010111001100000010001101111101101111100101110011000000100011111111111001111001011000110010001000111111111110011110010110001100100010000111111101100111100101100011001000100001011111011001111001011000110010001000110111110110011110010110001100100010001111111111101111100101100011001000100011111111 + 11111111111111111111111111111111T1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'controller:controller_0|rx_msg_captured' == high + + + + + + 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'mac_rgmii:mac_0|rx_sop' == high + + + + + + 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + 00000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000000000000000011000000000000000000101110111011101100101110110001000000100011000000010101000000000000000000001100000000000000000010111011101110110010111011000100000010001100000001010100000000000000000000110000000000000000001011101110111011001011101100010000001000110000000101010000000001000000111101000 + 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'mac_rgmii:mac_2|rx_ctl_m1[0]' == rising edge && 'mac_rgmii:mac_2|rx_ctl_m1[1]' == rising edge + + + + + + 111111111111111111111111111 + 111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 11111111111111111111111111111111 + 11111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'controller:controller_0|rx_msg_captured' == high + + + + + + 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + 000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000000000000000000000000000000000000000000000000000000011011100001000000000010010111010000000000000000010000000010000000000000000001111100000011111000000000000000000000000000000000000000000000000000000001101110000100000000001001011101000000000000000001000000001000000000000000000111110000001111100000000000000000000000000000000000000000000000000000000110111000010000000000100101110100000000000000000100000000100000000000000000011111000000111110000 + 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf new file mode 100644 index 0000000..9eba5e3 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf @@ -0,0 +1,114 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 192) + (text "ddrio" (rect 98 -2 136 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 177 24 188)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[7..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[7..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[7..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[7..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 81 39 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "inclocken" (rect 0 0 57 15)(font "Dialog" (font_size 8))) + (text "inclocken" (rect 4 97 51 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 0 128) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 113 47 127)(font "Dialog" (font_size 8))) + (line (pt 0 128)(pt 80 128)) + ) + (port + (pt 0 144) + (input) + (text "outclocken" (rect 0 0 67 15)(font "Dialog" (font_size 8))) + (text "outclocken" (rect 4 129 59 143)(font "Dialog" (font_size 8))) + (line (pt 0 144)(pt 80 144)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 145 23 159)(font "Dialog" (font_size 8))) + (line (pt 0 160)(pt 80 160)) + ) + (port + (pt 224 48) + (output) + (text "dataout_h[7..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[7..0]" (rect 158 33 235 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (port + (pt 224 64) + (output) + (text "dataout_l[7..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[7..0]" (rect 162 49 235 63)(font "Dialog" (font_size 8))) + (line (pt 224 64)(pt 144 64)(line_width 3)) + ) + (port + (pt 224 80) + (output) + (text "padio[7..0]" (rect 0 0 64 15)(font "Dialog" (font_size 8))) + (text "padio[7..0]" (rect 177 65 231 79)(font "Dialog" (font_size 8))) + (line (pt 224 80)(pt 144 80)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 176)) + (line (pt 80 176)(pt 144 176)) + (line (pt 80 32)(pt 80 176)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 192)) + (line (pt 0 192)(pt 224 192)) + (line (pt 0 0)(pt 0 192)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf new file mode 100644 index 0000000..03c4cef --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip new file mode 100644 index 0000000..b3dfeb4 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddrio.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v new file mode 100644 index 0000000..44b81db --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v @@ -0,0 +1,145 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] dataout_h = sub_wire0[7:0]; + wire [7:0] dataout_l = sub_wire1[7:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .padio (padio), + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .inclocken (inclocken), + .oe (oe), + .outclock (outclock), + .outclocken (outclocken), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .oe_out (), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "ON", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "ON", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "REGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 8; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v new file mode 100644 index 0000000..f489c24 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v @@ -0,0 +1,105 @@ +// megafunction wizard: %ALTDDIO_BIDIR%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v new file mode 100644 index 0000000..a999d47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v @@ -0,0 +1,13 @@ +ddrio ddrio_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .inclock ( inclock_sig ), + .inclocken ( inclocken_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .outclocken ( outclocken_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ), + .padio ( padio_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf b/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf new file mode 100644 index 0000000..0e82eda --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf @@ -0,0 +1,96 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 272 160) + (text "pll" (rect 129 0 144 15)(font "Arial" (font_size 10))) + (text "inst" (rect 8 145 24 156)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 52 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 48 64)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "areset" (rect 4 68 34 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 48 80)) + ) + (port + (pt 272 64) + (output) + (text "c0" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c0" (rect 255 52 266 63)(font "Arial" (font_size 8))) + ) + (port + (pt 272 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 255 68 266 79)(font "Arial" (font_size 8))) + ) + (port + (pt 272 96) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 232 84 263 95)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone 10 LP" (rect 186 147 430 303)(font "Arial" )) + (text "inclk0 frequency: 25.000 MHz" (rect 58 60 234 129)(font "Arial" )) + (text "Operation Mode: Normal" (rect 58 71 214 151)(font "Arial" )) + (text "Clk " (rect 59 89 131 187)(font "Arial" )) + (text "Ratio" (rect 80 89 180 187)(font "Arial" )) + (text "Ph (dg)" (rect 107 89 243 187)(font "Arial" )) + (text "DC (%)" (rect 143 89 315 187)(font "Arial" )) + (text "c0" (rect 62 101 133 211)(font "Arial" )) + (text "1/1" (rect 84 101 180 211)(font "Arial" )) + (text "0.00" (rect 113 101 243 211)(font "Arial" )) + (text "50.00" (rect 146 101 314 211)(font "Arial" )) + (text "c1" (rect 62 113 133 235)(font "Arial" )) + (text "5/1" (rect 84 113 180 235)(font "Arial" )) + (text "0.00" (rect 113 113 243 235)(font "Arial" )) + (text "50.00" (rect 146 113 314 235)(font "Arial" )) + (line (pt 0 0)(pt 273 0)) + (line (pt 273 0)(pt 273 161)) + (line (pt 0 161)(pt 273 161)) + (line (pt 0 0)(pt 0 161)) + (line (pt 56 87)(pt 176 87)) + (line (pt 56 98)(pt 176 98)) + (line (pt 56 110)(pt 176 110)) + (line (pt 56 122)(pt 176 122)) + (line (pt 56 87)(pt 56 122)) + (line (pt 77 87)(pt 77 122)(line_width 3)) + (line (pt 104 87)(pt 104 122)(line_width 3)) + (line (pt 140 87)(pt 140 122)(line_width 3)) + (line (pt 175 87)(pt 175 122)) + (line (pt 48 48)(pt 223 48)) + (line (pt 223 48)(pt 223 143)) + (line (pt 48 143)(pt 223 143)) + (line (pt 48 48)(pt 48 143)) + (line (pt 271 64)(pt 223 64)) + (line (pt 271 80)(pt 223 80)) + (line (pt 271 96)(pt 223 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf b/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf new file mode 100644 index 0000000..f563c40 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip b/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip new file mode 100644 index 0000000..5df3c41 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll.v new file mode 100644 index 0000000..cbe5878 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire3; + wire [0:0] sub_wire6 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire locked = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire3), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 5, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 40000, + altpll_component.intended_device_family = "Cyclone 10 LP", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v new file mode 100644 index 0000000..0f86c48 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v @@ -0,0 +1,232 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v new file mode 100644 index 0000000..6da79e5 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v @@ -0,0 +1,7 @@ +pll pll_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ), + .locked ( locked_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf new file mode 100644 index 0000000..c5f6b16 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf @@ -0,0 +1,65 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 208 96) + (text "ddri" (rect 93 -2 122 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 81 24 92)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain[4..0]" (rect 0 0 69 15)(font "Dialog" (font_size 8))) + (text "datain[4..0]" (rect 4 33 61 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 64 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 49 39 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 64 64)) + ) + (port + (pt 208 48) + (output) + (text "dataout_l[4..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[4..0]" (rect 146 33 219 47)(font "Dialog" (font_size 8))) + (line (pt 208 48)(pt 128 48)(line_width 3)) + ) + (port + (pt 208 64) + (output) + (text "dataout_h[4..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[4..0]" (rect 142 49 219 63)(font "Dialog" (font_size 8))) + (line (pt 208 64)(pt 128 64)(line_width 3)) + ) + (drawing + (line (pt 64 32)(pt 128 32)) + (line (pt 128 32)(pt 128 80)) + (line (pt 64 80)(pt 128 80)) + (line (pt 64 32)(pt 64 80)) + (line (pt 0 0)(pt 208 0)) + (line (pt 208 0)(pt 208 96)) + (line (pt 0 96)(pt 208 96)) + (line (pt 0 0)(pt 0 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp new file mode 100644 index 0000000..86f1250 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddri + PORT + ( + datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc new file mode 100644 index 0000000..3418b17 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc @@ -0,0 +1,26 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddri +( + datain[4..0], + inclock +) + +RETURNS ( + dataout_h[4..0], + dataout_l[4..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf new file mode 100644 index 0000000..b1742aa --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip new file mode 100644 index 0000000..18f0cc0 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_IN" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddri.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v new file mode 100644 index 0000000..f2d0c47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v @@ -0,0 +1,103 @@ +// megafunction wizard: %ALTDDIO_IN% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + + wire [4:0] sub_wire0; + wire [4:0] sub_wire1; + wire [4:0] dataout_h = sub_wire0[4:0]; + wire [4:0] dataout_l = sub_wire1[4:0]; + + altddio_in ALTDDIO_IN_component ( + .datain (datain), + .inclock (inclock), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .inclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_IN_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_IN_component.invert_input_clocks = "OFF", + ALTDDIO_IN_component.lpm_hint = "UNUSED", + ALTDDIO_IN_component.lpm_type = "altddio_in", + ALTDDIO_IN_component.power_up_high = "ON", + ALTDDIO_IN_component.width = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v new file mode 100644 index 0000000..ec7ac20 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v @@ -0,0 +1,74 @@ +// megafunction wizard: %ALTDDIO_IN%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v new file mode 100644 index 0000000..0574ba9 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v @@ -0,0 +1,6 @@ +ddri ddri_inst ( + .datain ( datain_sig ), + .inclock ( inclock_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf new file mode 100644 index 0000000..1cf5c0d --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 144) + (text "ddro" (rect 99 -2 133 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 129 24 140)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[5..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[5..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[5..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 81 47 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 97 23 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 224 48) + (output) + (text "dataout[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "dataout[5..0]" (rect 168 33 233 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 128)) + (line (pt 80 128)(pt 144 128)) + (line (pt 80 32)(pt 80 128)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 144)) + (line (pt 0 144)(pt 224 144)) + (line (pt 0 0)(pt 0 144)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp new file mode 100644 index 0000000..dbbc5a8 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddro + PORT + ( + aclr : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + oe : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc new file mode 100644 index 0000000..98c6145 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc @@ -0,0 +1,28 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddro +( + aclr, + datain_h[5..0], + datain_l[5..0], + oe, + outclock +) + +RETURNS ( + dataout[5..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf new file mode 100644 index 0000000..2d6a4da --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip new file mode 100644 index 0000000..3eb030b --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddro.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v new file mode 100644 index 0000000..87d2856 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v @@ -0,0 +1,115 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + + wire [5:0] sub_wire0; + wire [5:0] dataout = sub_wire0[5:0]; + + altddio_out ALTDDIO_OUT_component ( + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .oe (oe), + .outclock (outclock), + .dataout (sub_wire0), + .aset (1'b0), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 6; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v new file mode 100644 index 0000000..1529ff1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v @@ -0,0 +1,84 @@ +// megafunction wizard: %ALTDDIO_OUT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v new file mode 100644 index 0000000..32dfbbb --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v @@ -0,0 +1,8 @@ +ddro ddro_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .dataout ( dataout_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/mle_ram_0.txt b/manufacturer/altera/cyclone10_lp/mle_ram_0.txt new file mode 100644 index 0000000..9a9b3b2 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/mle_ram_0.txt @@ -0,0 +1,1024 @@ +077 +000 +000 +0FF // DEST MAC Address +0FF +0FF +0FF +0FF +0FF +002 // SRC MAC Address +00a +00b +00c +00d +00e +008 // Ether Type +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +080 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/manufacturer/altera/cyclone10_lp/mle_ram_1.txt b/manufacturer/altera/cyclone10_lp/mle_ram_1.txt new file mode 100644 index 0000000..dee4dca --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/mle_ram_1.txt @@ -0,0 +1,1024 @@ +000 +000 +000 +0FF // DEST MAC Address +0FF +0FF +0FF +0FF +0FF +002 // SRC MAC Address +00a +00b +00c +00d +00e +008 // Ether Type +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +080 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/param_ram_0.txt b/manufacturer/altera/cyclone10_lp/param_ram_0.txt new file mode 100644 index 0000000..726c29d --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/param_ram_0.txt @@ -0,0 +1,1024 @@ +000 +000 +000 +0FF // DEST MAC Address +0FF +0FF +0FF +0FF +0FF +002 // SRC MAC Address +00a +00b +00c +00d +001 +008 // Ether Type +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +080 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/param_ram_1.txt b/manufacturer/altera/cyclone10_lp/param_ram_1.txt new file mode 100644 index 0000000..dee4dca --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/param_ram_1.txt @@ -0,0 +1,1024 @@ +000 +000 +000 +0FF // DEST MAC Address +0FF +0FF +0FF +0FF +0FF +002 // SRC MAC Address +00a +00b +00c +00d +00e +008 // Ether Type +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +080 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/param_ram_2.txt b/manufacturer/altera/cyclone10_lp/param_ram_2.txt new file mode 100644 index 0000000..dee4dca --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/param_ram_2.txt @@ -0,0 +1,1024 @@ +000 +000 +000 +0FF // DEST MAC Address +0FF +0FF +0FF +0FF +0FF +002 // SRC MAC Address +00a +00b +00c +00d +00e +008 // Ether Type +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +080 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/.gitignore b/manufacturer/altera/cyclone10_lp/sim/.gitignore new file mode 100644 index 0000000..d2f09b4 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/.gitignore @@ -0,0 +1,12 @@ +aldec/ +libraries/ +work/ +rtl_work/ +vsim.wlf +wlf* +transcript +*.mti +*.orig +*.bak +tcl_* +msim_transcript diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat new file mode 100644 index 0000000..6f337f3 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat @@ -0,0 +1,145 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +0A +0B +0C +0D +0E +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 // Msg Type +ed // Token +07 // Address MSByte +00 // Address LSByte +00 // Data MSbyte +00 +00 +01 // Data LSbyte +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +20 // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +0A +0B +0C +0D +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +c3 // Token +00 // Address MSByte +10 // Address LSByte +01 // Data MSbyte +02 +03 +04 // Data LSbyte +00 // Pad +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat new file mode 100644 index 0000000..4590ab9 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat @@ -0,0 +1,145 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +0A +0B +0C +0D +0E +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +ed // Token +01 // Address MSByte +04 // Address LSByte +00 // Data MSbyte +00 +00 +00 // Data LSbyte +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +40 // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +0A +0B +0C +0D +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +c3 // Token +00 // Address MSByte +10 // Address LSByte +01 // Data MSbyte +02 +03 +04 // Data LSbyte +00 // Pad +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat new file mode 100644 index 0000000..2b9d4b1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat @@ -0,0 +1,72 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +07 // Msg Size +01 // Device +02 // Command +00 // Controller Address +02 // FW Increment +00 // Data +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +70 // FCS +E3 // +95 +1DA +40 // Idle Clocks \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat new file mode 100644 index 0000000..59e747a --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat @@ -0,0 +1,144 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +00 +00 +00 +00 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +00 +00 +00 +00 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat new file mode 100644 index 0000000..ca1df41 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat @@ -0,0 +1,144 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +00 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 +01 +01 +01 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat new file mode 100644 index 0000000..ad08f1b --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat @@ -0,0 +1,144 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL) +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +00 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 +02 +02 +02 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff \ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/lin/README b/manufacturer/altera/cyclone10_lp/sim/lin/README new file mode 100644 index 0000000..3aa3193 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/lin/README @@ -0,0 +1,33 @@ +GEODSS Simulation Project README + +Simulator: questa Intel edition + +questa project file: geodss_sim.mpf + +Run project by launching vsim in the questa_fse/bin directory and open project using File->Open + +In the command console: + +do geodss.do + +do wave.do // brings up nets suitable for viewing end-to-end packet transmission from Camera to Ethernet + +run 10 us + +Project Description: + +Simulation of the GEODSS Cyclone 10 GX FPGA project that includes all IP blocks. Project has been most recently updated for simulating end-to-end connectivity between Camera Fiber 1 (phy1) and Etherent (phy0) + +Test bench file is source/tb.sv and has support for emulating the camera's TX path into the FPGA's RX SERDES receiver with disparity accurate data. + +If the FPGA project is modified, then be sure to re-run Tools->Generate Simulator Simulator Script inside Quartus. + +Make sure the SIMULATION directive is defined for top.v and mac_geodss.v + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf b/manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf new file mode 100644 index 0000000..bc3671a --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf @@ -0,0 +1,2329 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "QA Baseline: 2021.1 Beta - 4536908" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = rtl_work +work_lib = ./libraries/work/ +ram_2port_2050 = ./libraries/ram_2port_2050 +dpram_2kx9 = ./libraries/dpram_2kx9 +altera_common_sv_packages = ./libraries/altera_common_sv_packages +altera_xcvr_atx_pll_a10_191 = ./libraries/altera_xcvr_atx_pll_a10_191 +gige_pll_atx = ./libraries/gige_pll_atx +altera_xcvr_fpll_a10_191 = ./libraries/altera_xcvr_fpll_a10_191 +gige_pll_fract = ./libraries/gige_pll_fract +altera_xcvr_reset_control_1911 = ./libraries/altera_xcvr_reset_control_1911 +gige_reset_cont = ./libraries/gige_reset_cont +altera_xcvr_native_a10_1911 = ./libraries/altera_xcvr_native_a10_1911 +gige_xcvr = ./libraries/gige_xcvr +altera_int_osc_1910 = ./libraries/altera_int_osc_1910 +internal_osc = ./libraries/internal_osc +param_ram = ./libraries/param_ram +sgmii_xcvr = ./libraries/sgmii_xcvr +altera_temp_sense_1910 = ./libraries/altera_temp_sense_1910 +temp_sensor = ./libraries/temp_sensor +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = [,]{:[,]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 10 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-][,[+|-]]*" +' Valid settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-]