From 70cc96d7a94f6ceabde7de511c28db7bc4536278 Mon Sep 17 00:00:00 2001 From: mindchasers Date: Tue, 2 Mar 2021 13:10:45 -0500 Subject: spi: fix write bug --- source/spi.v | 63 +++++++++++++++++++++++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/source/spi.v b/source/spi.v index 7d6004e..d7c054b 100644 --- a/source/spi.v +++ b/source/spi.v @@ -1,7 +1,7 @@ /* * spi.v * - * Copyright (C) 2018, 2019 Mind Chasers Inc. + * Copyright (C) 2018, 2019, 2020, 2021 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,8 +18,7 @@ * function: SPI slave controller * * refer to SPI protocol figure at https://mindchasers.com/dev/hw-spi - * - * + * */ `timescale 1ns /10ps @@ -72,7 +71,8 @@ wire bit_cnt_rstn; // async reset at start of SPI cycle reg spi_clk_m1, spi_clk_m2; // detect / debounce the SPI CLK - reg spi_clk_high, spi_clk_high_m1; // one shot clocks for sequencing events + reg spi_clk_high, spi_clk_high_m1; // one shot clocks for sequencing events + reg spi_clk_low, spi_clk_low_m1; // one shot clocks for sequencing events reg [4:0] bit_cnt; // cnt the bits reg [6:0] word_cnt; // number of bytes transferred, OK to roll over @@ -119,6 +119,25 @@ spi_clk_high_m1 <= spi_clk_high; end + + // create two seq one shots for actions + always @(posedge clk or negedge bit_cnt_rstn) + begin + if ( !bit_cnt_rstn ) + spi_clk_low <= 0; + else if ( spi_cs && spi_clk && !spi_clk_m1 && spi_clk_m2 ) + spi_clk_low <= 1'b1; + else + spi_clk_low <= 1'b0; + end + + always @(posedge clk or negedge bit_cnt_rstn) + begin + if ( !bit_cnt_rstn ) + spi_clk_low_m1 <= 0; + else + spi_clk_low_m1 <= spi_clk_low; + end /* bit_cnt indicates the state of the SPI transfer @@ -132,7 +151,7 @@ begin if ( !bit_cnt_rstn ) bit_cnt <= 5'h0; - else if ( spi_cs && spi_clk_high ) begin + else if ( spi_cs && spi_clk_high_m1 ) begin if ( bit_cnt == 5'd26 ) bit_cnt <= 5'd18; else @@ -198,44 +217,40 @@ // we always @(posedge clk or negedge bit_cnt_rstn) - begin if (!bit_cnt_rstn) we <= 1'b0; - else if ( spi_cs ) begin - if ( spi_clk_high && !rwn && bit_cnt == 5'd25 ) + else if ( spi_cs ) + if ( spi_clk_high && !rwn && bit_cnt == 5'd26 ) we <= 1'b1; else we <= 1'b0; - end; - end /* SPI data output enable */ assign spi_d_oe = spi_cs; /* - * clock out msb first. - * First bit comes out on cs + * clock out msb first. + * */ always @(posedge clk or negedge bit_cnt_rstn) - begin if ( !bit_cnt_rstn ) spi_d_o <= start_code[8]; else if ( spi_cs && spi_clk_high_m1 ) begin if ( bit_cnt < 9 ) spi_d_o <= start_code['d8 - bit_cnt[3:0]]; - else if ( !rwn && bit_cnt >= 'd18 ) - spi_d_o <= word_cnt['d8 - bit_cnt[3:0]]; - else if ( rwn && bit_cnt >= 'd18 ) - spi_d_o <= d_i['d8 - bit_cnt[3:0]]; - else + else if ( !rwn && bit_cnt >= 'd18 && bit_cnt < 'd26 ) + spi_d_o <= word_cnt['d25-bit_cnt]; + else if ( rwn && bit_cnt >= 'd18 && bit_cnt < 'd26 ) + spi_d_o <= d_i['d25-bit_cnt]; + else spi_d_o <= 1'b0; end - end - - assign oe = ( (dpram_rx_sel || dpram_tx_sel) && rwn) ? 1'b1 : 1'b0; - - + else if (spi_cs && spi_clk_high_m1 && rwn && bit_cnt == 'd26) + spi_d_o <= d_i[8]; + + assign oe = mem_sel && rwn; + /* Address Decoding */ assign pkt_filter_sel = pkt_filter_sel_01 | pkt_filter_sel_02 | pkt_filter_sel_10 | pkt_filter_sel_12 | pkt_filter_sel_20 | pkt_filter_sel_21 | pkt_filter_sel_23; @@ -297,4 +312,4 @@ end endmodule - + \ No newline at end of file -- cgit v1.2.3-8-gadcc