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<title>privateisland/manufacturer/altera/cyclone10_lp, branch gpio</title>
<subtitle>Open Source FPGA Verilog Project for Networking</subtitle>
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<updated>2026-07-06T18:00:38Z</updated>
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<title>project: add gpio revision to support daughter board I/O renaming</title>
<updated>2026-07-06T18:00:38Z</updated>
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<name>Private Island Networks Inc.</name>
<email>opensource@privateisland.tech</email>
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<published>2026-07-06T18:00:38Z</published>
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<title>src: modify gpio i/o size, replace hard addresses with params, misc fix ups</title>
<updated>2026-07-06T17:58:40Z</updated>
<author>
<name>Private Island Networks Inc.</name>
<email>opensource@privateisland.tech</email>
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<published>2026-07-06T17:58:40Z</published>
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<title>gpio: first pass changes to support new GPIO daughter board</title>
<updated>2026-07-01T19:48:33Z</updated>
<author>
<name>Jacob Corder</name>
<email>jacob@privateisland.tech</email>
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<published>2026-07-01T19:48:33Z</published>
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<title>mle: patch files to support FSM3, MLE header, and bug fixes</title>
<updated>2026-02-03T20:58:01Z</updated>
<author>
<name>Private Island Networks Inc</name>
<email>opensource@privateisland.tech</email>
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<published>2026-02-03T20:58:01Z</published>
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<title>betsy: preliminary beta snapshot</title>
<updated>2025-12-22T01:51:04Z</updated>
<author>
<name>Private Island Networks Inc</name>
<email>opensource@privateisland.tech</email>
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<published>2025-12-22T01:51:04Z</published>
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