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<title>ml_module_agilex3/fpga_banks_6f_6g_6h.kicad_sch, branch master</title>
<subtitle>ML Module using Agilex 3 for Betsy, KiCad Project</subtitle>
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<updated>2026-06-05T23:46:16Z</updated>
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<title>update Agliex footprint and symbol, all schematic pages, move bank 3A to lpddr, create initial FPGA trace, import power circuit</title>
<updated>2026-06-05T23:46:16Z</updated>
<author>
<name>Private Island Networks Inc.</name>
<email>opensource@privateisland.tech</email>
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<published>2026-06-05T23:46:16Z</published>
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<entry>
<title>project: create starting sheets for project and populate FPGA banks</title>
<updated>2026-05-19T17:02:52Z</updated>
<author>
<name>Private Island Networks Inc.</name>
<email>opensource@privateisland.tech</email>
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<published>2026-05-19T17:02:52Z</published>
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