proc get_design_libraries {} {
  set libraries [dict create]
  dict set libraries altera_iopll_2110           1
  dict set libraries pll_io                      1
  dict set libraries altera_gpio_core10_ph2_2210 1
  dict set libraries altera_gpio_2300            1
  dict set libraries ddr_o                       1
  dict set libraries ddr_i                       1
  return $libraries
}

proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
  set memory_files [list]
  return $memory_files
}

proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
  set design_files [dict create]
  return $design_files
}

proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
  set design_files [list]
  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/pll_io/altera_iopll_2110/sim/pll_io_altera_iopll_2110_txusefy.vo"]\"  -work altera_iopll_2110"  
  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/pll_io/sim/pll_io.v"]\"  -work pll_io"                                                          
  lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/altera_gpio_core10_ph2_2210/sim/altera_gpio.sv"]\"  -work altera_gpio_core10_ph2_2210"
  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/altera_gpio_2300/sim/ddr_o_altera_gpio_2300_hykp5oy.v"]\"  -work altera_gpio_2300"        
  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/sim/ddr_o.v"]\"  -work ddr_o"                                                             
  lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/altera_gpio_core10_ph2_2210/sim/altera_gpio.sv"]\"  -work altera_gpio_core10_ph2_2210"
  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/altera_gpio_2300/sim/ddr_i_altera_gpio_2300_iejxysy.v"]\"  -work altera_gpio_2300"        
  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/sim/ddr_i.v"]\"  -work ddr_i"                                                             
  return $design_files
}

proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
  set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
  if {$IS_DUPLICATE == -1} {
    return $NEW_ELAB_OPTION
  } else {
    return ""
  }
}


proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
  set ELAB_OPTIONS ""
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $ELAB_OPTIONS
}


proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
  set SIM_OPTIONS ""
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $SIM_OPTIONS
}


proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
  set ENV_VARIABLES [dict create]
  set LD_LIBRARY_PATH [dict create]
  dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $ENV_VARIABLES
}


proc normalize_path {FILEPATH} {
    if {[catch { package require fileutil } err]} { 
        return $FILEPATH 
    } 
    set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
    if {[file pathtype $FILEPATH] eq "relative"} { 
        set path [fileutil::relative [pwd] $path] 
    } 
    return $path 
} 
proc get_dpi_libraries {QSYS_SIMDIR} {
  set libraries [dict create]
  
  return $libraries
}