create_clock -name clk -period 40.0 [get_ports clk_i];

create_clock -name rgmii_rx_clk_v -period 8.0; # virtual clock for input constraint timing
create_clock -name rgmii_rx_clk -period 8.0 -waveform { 2 6 } [get_ports rgmii_rx_clk];

create_clock -name rgmii_tx_clk -period 8.0 [get_ports rgmii_tx_clk];
create_clock -name rgmii_tx_clk_v -period 8.0; # virtual clock for input constraint timing

derive_pll_clocks -create_base_clocks -use_net_name

# RGMII Input Clock
set_input_delay -min -0.8 -clock { rgmii_rx_clk_v } [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay
set_input_delay -min -0.8 -clock { rgmii_rx_clk_v } -clock_fall [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay

set_input_delay -max 0.8 -clock { rgmii_rx_clk_v } [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay 
set_input_delay -max 0.8 -clock { rgmii_rx_clk_v } -clock_fall [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay

# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks rgmii_rx_clk_v] -rise_to [get_clocks {rgmii_rx_clk}] -setup
set_false_path -rise_from [get_clocks rgmii_rx_clk_v] -fall_to [get_clocks {rgmii_rx_clk}] -setup
set_false_path -fall_from [get_clocks rgmii_rx_clk_v] -fall_to [get_clocks {rgmii_rx_clk}] -hold
set_false_path -rise_from [get_clocks rgmii_rx_clk_v] -rise_to [get_clocks {rgmii_rx_clk}] -hold

set_output_delay -max 0.5 -clock { rgmii_tx_clk } [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay
set_output_delay -max 0.5 -clock { rgmii_tx_clk } -clock_fall [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay

set_output_delay -min -0.5 -clock { rgmii_tx_clk } [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { rgmii_tx_clk } -clock_fall [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay