From 694f71a280c7c386a7f9c6dcc220563fe7b61313 Mon Sep 17 00:00:00 2001 From: Private Island Networks Inc Date: Wed, 13 May 2026 12:52:39 -0400 Subject: initial commit, see README in top folder --- sim/win/.gitignore | 1 + sim/win/common/modelsim_files.tcl | 90 ++ sim/win/elab.do | 66 ++ sim/win/mentor/msim_setup.tcl | 441 +++++++ sim/win/mentor/run_msim_setup.tcl | 36 + sim/win/ml_module.mpf | 2300 +++++++++++++++++++++++++++++++++++++ sim/win/modelsim.ini | 2237 ++++++++++++++++++++++++++++++++++++ sim/win/sim.do | 2 + 8 files changed, 5173 insertions(+) create mode 100644 sim/win/.gitignore create mode 100644 sim/win/common/modelsim_files.tcl create mode 100644 sim/win/elab.do create mode 100644 sim/win/mentor/msim_setup.tcl create mode 100644 sim/win/mentor/run_msim_setup.tcl create mode 100644 sim/win/ml_module.mpf create mode 100644 sim/win/modelsim.ini create mode 100644 sim/win/sim.do (limited to 'sim/win') diff --git a/sim/win/.gitignore b/sim/win/.gitignore new file mode 100644 index 0000000..2211df6 --- /dev/null +++ b/sim/win/.gitignore @@ -0,0 +1 @@ +*.txt diff --git a/sim/win/common/modelsim_files.tcl b/sim/win/common/modelsim_files.tcl new file mode 100644 index 0000000..0dd16b2 --- /dev/null +++ b/sim/win/common/modelsim_files.tcl @@ -0,0 +1,90 @@ + +proc get_design_libraries {} { + set libraries [dict create] + dict set libraries altera_iopll_2110 1 + dict set libraries pll_io 1 + dict set libraries altera_gpio_core10_ph2_2210 1 + dict set libraries altera_gpio_2300 1 + dict set libraries ddr_o 1 + dict set libraries ddr_i 1 + return $libraries +} + +proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} { + set memory_files [list] + return $memory_files +} + +proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} { + set design_files [dict create] + return $design_files +} + +proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} { + set design_files [list] + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/pll_io/altera_iopll_2110/sim/pll_io_altera_iopll_2110_txusefy.vo"]\" -work altera_iopll_2110" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/pll_io/sim/pll_io.v"]\" -work pll_io" + lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/altera_gpio_core10_ph2_2210/sim/altera_gpio.sv"]\" -work altera_gpio_core10_ph2_2210" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/altera_gpio_2300/sim/ddr_o_altera_gpio_2300_hykp5oy.v"]\" -work altera_gpio_2300" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/sim/ddr_o.v"]\" -work ddr_o" + lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/altera_gpio_core10_ph2_2210/sim/altera_gpio.sv"]\" -work altera_gpio_core10_ph2_2210" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/altera_gpio_2300/sim/ddr_i_altera_gpio_2300_iejxysy.v"]\" -work altera_gpio_2300" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/sim/ddr_i.v"]\" -work ddr_i" + return $design_files +} + +proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} { + set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS] + if {$IS_DUPLICATE == -1} { + return $NEW_ELAB_OPTION + } else { + return "" + } +} + + +proc get_elab_options {SIMULATOR_TOOL_BITNESS} { + set ELAB_OPTIONS "" + if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] { + } else { + } + return $ELAB_OPTIONS +} + + +proc get_sim_options {SIMULATOR_TOOL_BITNESS} { + set SIM_OPTIONS "" + if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] { + } else { + } + return $SIM_OPTIONS +} + + +proc get_env_variables {SIMULATOR_TOOL_BITNESS} { + set ENV_VARIABLES [dict create] + set LD_LIBRARY_PATH [dict create] + dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH + if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] { + } else { + } + return $ENV_VARIABLES +} + + +proc normalize_path {FILEPATH} { + if {[catch { package require fileutil } err]} { + return $FILEPATH + } + set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]] + if {[file pathtype $FILEPATH] eq "relative"} { + set path [fileutil::relative [pwd] $path] + } + return $path +} +proc get_dpi_libraries {QSYS_SIMDIR} { + set libraries [dict create] + + return $libraries +} + diff --git a/sim/win/elab.do b/sim/win/elab.do new file mode 100644 index 0000000..1175739 --- /dev/null +++ b/sim/win/elab.do @@ -0,0 +1,66 @@ +# +# file: sim.do +# +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +set QSYS_SIMDIR . + +# # +# # Source the generated IP simulation script. + +source $QSYS_SIMDIR/mentor/msim_setup.tcl + +# # +# # Set any compilation options you require (this is unusual). +# set USER_DEFINED_COMPILE_OPTIONS +# set USER_DEFINED_VHDL_COMPILE_OPTIONS +# set USER_DEFINED_VERILOG_COMPILE_OPTIONS +# # +# # Call command to compile the Quartus EDA simulation library. + +dev_com + +# # +# # Call command to compile the Quartus-generated IP simulation files. + +com + +# # +# # Add commands to compile all design files and testbench files, including +# # the top level. (These are all the files required for simulation other +# # than the files compiled by the Quartus-generated IP simulation script) +# # + +vlog -work work -vopt +define+SIMULATION ../../src/ml_module_agilex.v +vlog -work work ../src/tb.sv + +# # +# # Set the top-level simulation or testbench module/entity name, which is +# # used by the elab command to elaborate the top level. +# # + +set TOP_LEVEL_NAME tb + +# # +# # Set any elaboration options you require. +set USER_DEFINED_ELAB_OPTIONS -voptargs=+acc +# # +# # Call command to elaborate your design and testbench. + +elab + +# # +# # Run the simulation. +# run -a +# # +# # Report success to the shell. +# exit -code 0 +# # + diff --git a/sim/win/mentor/msim_setup.tcl b/sim/win/mentor/msim_setup.tcl new file mode 100644 index 0000000..240bb0b --- /dev/null +++ b/sim/win/mentor/msim_setup.tcl @@ -0,0 +1,441 @@ + +# (C) 2001-2026 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Intel +# Program License Subscription Agreement, Intel MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Intel and sold by Intel +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ---------------------------------------- +# Auto-generated simulation script msim_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# pll_io.pll_io +# ddr_o.ddr_o +# ddr_i.ddr_i +# +# Intel recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Intel simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "mentor.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR