From 694f71a280c7c386a7f9c6dcc220563fe7b61313 Mon Sep 17 00:00:00 2001 From: Private Island Networks Inc Date: Wed, 13 May 2026 12:52:39 -0400 Subject: initial commit, see README in top folder --- ip/pll_io.ip | 1816 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1816 insertions(+) create mode 100644 ip/pll_io.ip (limited to 'ip/pll_io.ip') diff --git a/ip/pll_io.ip b/ip/pll_io.ip new file mode 100644 index 0000000..84caf8f --- /dev/null +++ b/ip/pll_io.ip @@ -0,0 +1,1816 @@ + + + + Altera + pll_io + iopll_0 + 21.1.0 + + + refclk + + + + + + + + clk + + + refclk + + + + + + + + + clockRate + Clock rate + 25000000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + input + + + + + + + locked + + + + + + + + export + + + locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + reset + + + + + + + + reset + + + rst + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + ui.blockdiagram.direction + input + + + + + + + outclk0 + + + + + + + + clk + + + outclk_0 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 25000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk1 + + + + + + + + clk + + + outclk_1 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_iopll + + QUARTUS_SYNTH + + + + + + refclk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_0 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_1 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera + pll_io + altera_iopll + 21.1.0 + + + + + gui_debug_mode + + false + + + gui_skip_sdc_generation + + false + + + gui_include_iossm + + false + + + gui_cal_code_hex_file + + iossm.hex + + + gui_parameter_table_hex_file + + seq_params_sim.hex + + + gui_pll_tclk_mux_en + + false + + + gui_pll_tclk_sel + + pll_tclk_m_src + + + gui_pll_vco_freq_band_0 + + pll_freq_clk0_band18 + + + gui_pll_vco_freq_band_1 + + pll_freq_clk1_band18 + + + gui_pll_freqcal_en + + true + + + gui_pll_freqcal_req_flag + + true + + + gui_cal_converge + + false + + + gui_cal_error + + cal_clean + + + gui_pll_cal_done + + false + + + gui_pll_type + + S10_Physical + + + gui_pll_m_cnt_in_src + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src0 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src1 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src2 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src3 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src4 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src5 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src6 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src7 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src8 + + c_m_cnt_in_src_ph_mux_clk + + + system_info_device_family + Device Family + Agilex 3 + + + system_info_device_component + Component + A3CY050BB18AI6S + + + system_info_device_iobank_rev + IO Bank Revision + + + + system_part_trait_speed_grade + Speed Grade Trait + 6 + + + system_part_trait_iobank_rev + IO Bank Revision Trait + IO96B_REVB1 + + + system_info_device_speed_grade + Speed Grade + 5 + + + gui_usr_device_speed_grade + Speed Grade + 1 + + + gui_en_reconf + Enable dynamic reconfiguration of PLL + false + + + gui_en_hvio_reconf + Enable dynamic reconfiguration of PLL + false + + + gui_en_iossm_reconf + Enable dynamic reconfiguration of PLL using Calibration IP + false + + + gui_user_base_address + User base address of PLL for dynamic reconfiguration (0..255) + 0 + + + gui_en_dps_ports + Enable access to dynamic phase shift ports + false + + + gui_pll_mode + PLL Mode + Integer-N PLL + + + gui_location_type + IOPLL Type + I/O Bank + + + gui_use_logical + Use logical PLL + false + + + gui_reference_clock_frequency + Reference Clock Frequency + 25.0 + + + gui_reference_clock_frequency_ps + Reference Clock Frequency + 40000.0 + + + gui_use_coreclk + Refclk source is global clock + false + + + gui_refclk_might_change + My reference clock frequency might change + false + + + gui_fractional_cout + Fractional carry out + 24 + + + gui_prot_mode + prot_mode + UNUSED + + + gui_dsm_out_sel + DSM Order + 1st_order + + + gui_use_locked + Enable 'locked' output port + true + + + gui_set_locked_as_reset + Set 'locked' as reset interface + false + + + gui_en_adv_params + Enable physical output clock parameters + false + + + gui_use_fractional_division + Enable fractional division + false + + + gui_pll_bandwidth_preset + PLL Bandwidth Preset + Low + + + gui_lock_setting + Lock Threshold Setting + Low Lock Time + + + gui_pll_auto_reset + PLL Auto Reset + false + + + gui_en_lvds_ports + Access to PLL LVDS_CLK/LOADEN output port + Disabled + + + gui_en_periphery_ports + Enable access to I/O Bank clock ports + false + + + gui_operation_mode + Compensation Mode + direct + + + gui_feedback_clock + Feedback Clock + Global Clock + + + gui_clock_to_compensate + Compensated Outclk + 0 + + + gui_use_NDFB_modes + Use Nondedicated Feedback Path + false + + + gui_refclk_switch + Create a second input clock signal 'refclk1' + false + + + gui_refclk1_frequency + Second Reference Clock Frequency + 100.0 + + + gui_en_phout_ports + Enable access to PLL DPA output port + false + + + gui_phout_division + PLL DPA output division + 1 + + + gui_en_extclkout_ports + Enable access to PLL external clock output port + false + + + gui_number_of_clocks + Number Of Clocks + 2 + + + gui_multiply_factor + Multiply Factor (M-Counter) + 6 + + + gui_multiply_fraction + Multiply Factor (Fraction) + 0 + + + gui_use_slvs_refclk + Use SLVS400 for the PLL reference clock + false + + + gui_use_slvs_refclk1 + Use SLVS400 for the second PLL reference clock + false + + + gui_divide_factor_n + Divide Factor (N-Counter) + 1 + + + gui_frac_multiply_factor + Fractional Multiply Factor (K) + 0 + + + gui_fix_vco_frequency + Specify VCO frequency + false + + + gui_fixed_vco_frequency + Desired VCO Frequency + 600.0 + + + gui_fixed_vco_frequency_ps + Desired VCO Frequency + 1667.0 + + + gui_vco_frequency + Actual VCO Frequency + 600.0 + + + gui_enable_output_counter_cascading + Enable output counter cascading + false + + + gui_mif_gen_options + MIF Generation Options + Generate New MIF File + + + gui_new_mif_file_path + Path to New MIF file + ~/pll.mif + + + gui_existing_mif_file_path + Path to Existing MIF file + ~/pll.mif + + + gui_mif_config_name + Name of Current Configuration + unnamed + + + gui_active_clk + Create an 'active_clk' signal to indicate the input clock in use + false + + + gui_clk_bad + Create a 'clkbad' signal for each of the input clocks + false + + + gui_switchover_mode + Switchover Mode + Automatic Switchover + + + gui_switchover_delay + Switchover Delay + 0 + + + gui_enable_cascade_out + Create a 'cascade_out' signal to connect to a downstream PLL + false + + + gui_cascade_outclk_index + cascade_out source + 5 + + + gui_enable_cascade_in + Create an 'adjpllin' (cascade in) signal to connect to an upstream PLL through IO Column Cascading + false + + + gui_enable_permit_cal + Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal input signal) + false + + + gui_enable_upstream_out_clk + Connect outclk to a downstream PLL through Core Clock Network Cascading + false + + + gui_pll_cascading_mode + Connection Signal Type to Upstream PLL + adjpllin + + + gui_enable_mif_dps + Enable Dynamic Phase Shift for MIF streaming + false + + + gui_dps_cntr + DPS Counter Selection + C0 + + + gui_dps_num + Number of Dynamic Phase Shifts + 1 + + + gui_dps_dir + Dynamic Phase Shift Direction + Positive + + + gui_extclkout_0_source + extclk_out[0] source + C0 + + + gui_extclkout_1_source + extclk_out[1] source + C0 + + + gui_extclkout_source + extclk_out source + C0 + + + gui_clock_name_global + Give clocks global names + false + + + gui_clock_name_instantiation + Use clock names as ports in instantiation + false + + + gui_clock_name_string0 + Clock Name + outclk0 + + + gui_clock_name_string1 + Clock Name + outclk1 + + + gui_clock_name_string2 + Clock Name + outclk2 + + + gui_clock_name_string3 + Clock Name + outclk3 + + + gui_clock_name_string4 + Clock Name + outclk4 + + + gui_clock_name_string5 + Clock Name + outclk5 + + + gui_clock_name_string6 + Clock Name + outclk6 + + + gui_clock_name_string7 + Clock Name + outclk7 + + + gui_clock_name_string8 + Clock Name + outclk8 + + + gui_clock_name_string9 + Clock Name + outclk9 + + + gui_clock_name_string10 + Clock Name + outclk10 + + + gui_clock_name_string11 + Clock Name + outclk11 + + + gui_clock_name_string12 + Clock Name + outclk12 + + + gui_clock_name_string13 + Clock Name + outclk13 + + + gui_clock_name_string14 + Clock Name + outclk14 + + + gui_clock_name_string15 + Clock Name + outclk15 + + + gui_clock_name_string16 + Clock Name + outclk16 + + + gui_clock_name_string17 + Clock Name + outclk17 + + + gui_divide_factor_c0 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c1 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c2 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c3 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c4 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c5 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c6 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c7 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c8 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c9 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c10 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c11 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c12 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c13 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c14 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c15 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c16 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c17 + Divide Factor (C-Counter) + 6 + + + gui_cascade_counter0 + Make this a cascade counter + false + + + gui_cascade_counter1 + Make this a cascade counter + false + + + gui_cascade_counter2 + Make this a cascade counter + false + + + gui_cascade_counter3 + Make this a cascade counter + false + + + gui_cascade_counter4 + Make this a cascade counter + false + + + gui_cascade_counter5 + Make this a cascade counter + false + + + gui_cascade_counter6 + Make this a cascade counter + false + + + gui_cascade_counter7 + Make this a cascade counter + false + + + gui_cascade_counter8 + Make this a cascade counter + false + + + gui_cascade_counter9 + Make this a cascade counter + false + + + gui_cascade_counter10 + Make this a cascade counter + false + + + gui_cascade_counter11 + Make this a cascade counter + false + + + gui_cascade_counter12 + Make this a cascade counter + false + + + gui_cascade_counter13 + Make this a cascade counter + false + + + gui_cascade_counter14 + Make this a cascade counter + false + + + gui_cascade_counter15 + Make this a cascade counter + false + + + gui_cascade_counter16 + Make this a cascade counter + false + + + gui_cascade_counter17 + Make this a cascade counter + false + + + gui_output_clock_frequency0 + Desired Frequency + 25.0 + + + gui_output_clock_frequency1 + Desired Frequency + 125.0 + + + gui_output_clock_frequency2 + Desired Frequency + 100.0 + + + gui_output_clock_frequency3 + Desired Frequency + 100.0 + + + gui_output_clock_frequency4 + Desired Frequency + 100.0 + + + gui_output_clock_frequency5 + Desired Frequency + 100.0 + + + gui_output_clock_frequency6 + Desired Frequency + 100.0 + + + gui_output_clock_frequency7 + Desired Frequency + 100.0 + + + gui_output_clock_frequency8 + Desired Frequency + 100.0 + + + gui_output_clock_frequency9 + Desired Frequency + 100.0 + + + gui_output_clock_frequency10 + Desired Frequency + 100.0 + + + gui_output_clock_frequency11 + Desired Frequency + 100.0 + + + gui_output_clock_frequency12 + Desired Frequency + 100.0 + + + gui_output_clock_frequency13 + Desired Frequency + 100.0 + + + gui_output_clock_frequency14 + Desired Frequency + 100.0 + + + gui_output_clock_frequency15 + Desired Frequency + 100.0 + + + gui_output_clock_frequency16 + Desired Frequency + 100.0 + + + gui_output_clock_frequency17 + Desired Frequency + 100.0 + + + gui_output_clock_frequency_ps0 + Desired Frequency + 40000.0 + + + gui_output_clock_frequency_ps1 + Desired Frequency + 8000.0 + + + gui_output_clock_frequency_ps2 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps3 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps4 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps5 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps6 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps7 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps8 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps9 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps10 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps11 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps12 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps13 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps14 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps15 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps16 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps17 + Desired Frequency + 10000.0 + + + gui_ps_units0 + Phase Shift Units + ps + + + gui_ps_units1 + Phase Shift Units + ps + + + gui_ps_units2 + Phase Shift Units + ps + + + gui_ps_units3 + Phase Shift Units + ps + + + gui_ps_units4 + Phase Shift Units + ps + + + gui_ps_units5 + Phase Shift Units + ps + + + gui_ps_units6 + Phase Shift Units + ps + + + gui_ps_units7 + Phase Shift Units + ps + + + gui_ps_units8 + Phase Shift Units + ps + + + gui_ps_units9 + Phase Shift Units + ps + + + gui_ps_units10 + Phase Shift Units + ps + + + gui_ps_units11 + Phase Shift Units + ps + + + gui_ps_units12 + Phase Shift Units + ps + + + gui_ps_units13 + Phase Shift Units + ps + + + gui_ps_units14 + Phase Shift Units + ps + + + gui_ps_units15 + Phase Shift Units + ps + + + gui_ps_units16 + Phase Shift Units + ps + + + gui_ps_units17 + Phase Shift Units + ps + + + gui_phase_shift0 + Desired Phase Shift + 0.0 + + + gui_phase_shift1 + Desired Phase Shift + 0.0 + + + gui_phase_shift2 + Desired Phase Shift + 0.0 + + + gui_phase_shift3 + Desired Phase Shift + 0.0 + + + gui_phase_shift4 + Desired Phase Shift + 0.0 + + + gui_phase_shift5 + Desired Phase Shift + 0.0 + + + gui_phase_shift6 + Desired Phase Shift + 0.0 + + + gui_phase_shift7 + Desired Phase Shift + 0.0 + + + gui_phase_shift8 + Desired Phase Shift + 0.0 + + + gui_phase_shift9 + Desired Phase Shift + 0.0 + + + gui_phase_shift10 + Desired Phase Shift + 0.0 + + + gui_phase_shift11 + Desired Phase Shift + 0.0 + + + gui_phase_shift12 + Desired Phase Shift + 0.0 + + + gui_phase_shift13 + Desired Phase Shift + 0.0 + + + gui_phase_shift14 + Desired Phase Shift + 0.0 + + + gui_phase_shift15 + Desired Phase Shift + 0.0 + + + gui_phase_shift16 + Desired Phase Shift + 0.0 + + + gui_phase_shift17 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg0 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg1 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg2 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg3 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg4 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg5 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg6 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg7 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg8 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg9 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg10 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg11 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg12 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg13 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg14 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg15 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg16 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg17 + Desired Phase Shift + 0.0 + + + gui_duty_cycle0 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle1 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle2 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle3 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle4 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle5 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle6 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle7 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle8 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle9 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle10 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle11 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle12 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle13 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle14 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle15 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle16 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle17 + Desired Duty Cycle + 50.0 + + + gui_simulation_type + Force full PLL simulation model + true + + + hp_qsys_scripting_mode + hp_qsys_scripting_mode + false + + + + + + + embeddedsw.dts.compatible + altr,pll + + + embeddedsw.dts.group + clock + + + embeddedsw.dts.vendor + altr + + + + + + + board + Board + default + + + device + Device + A3CY050BB18AI6S + + + deviceFamily + Device family + Agilex 3 + + + deviceSpeedGrade + Device Speed Grade + 6 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element iopll_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>outclk0</key> + <value> + <connectionPointName>outclk0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>25000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk1</key> + <value> + <connectionPointName>outclk1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file -- cgit v1.2.3-8-gadcc