From 694f71a280c7c386a7f9c6dcc220563fe7b61313 Mon Sep 17 00:00:00 2001 From: Private Island Networks Inc Date: Wed, 13 May 2026 12:52:39 -0400 Subject: initial commit, see README in top folder --- ip/ddr_o.ip | 446 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 446 insertions(+) create mode 100644 ip/ddr_o.ip (limited to 'ip/ddr_o.ip') diff --git a/ip/ddr_o.ip b/ip/ddr_o.ip new file mode 100644 index 0000000..285625a --- /dev/null +++ b/ip/ddr_o.ip @@ -0,0 +1,446 @@ + + + + Altera + ddr_o + gpio_0 + 23.0.0 + + + ck + + + + + + + + export + + + ck + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + din + + + + + + + + export + + + din + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + pad_out + + + + + + + + export + + + pad_out + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_gpio + + QUARTUS_SYNTH + + + + + + ck + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + din + + in + + + 0 + 11 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + pad_out + + out + + + 0 + 5 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Altera + ddr_o + altera_gpio + 23.0.0 + + + + + device_family + device_family + Agilex 3 + + + PIN_TYPE_GUI + Data Direction + Output + + + SIZE + Data width + 6 + + + gui_enable_migratable_port_names + Use legacy top-level port names + false + + + gui_diff_buff + Use differential buffer + false + + + gui_pseudo_diff + Use pseudo-differential buffer + false + + + gui_bus_hold + Use bus-hold circuitry + false + + + gui_open_drain + Use open-drain output + false + + + gui_use_oe + Enable output enable port + false + + + gui_enable_termination_ports + Enable seriestermination/paralleltermination ports + false + + + gui_use_puen + Enable dynamic pull-up port + false + + + gui_io_reg_mode + Register mode + DDIO + + + gui_sreset_mode + Enable synchronous clear / preset port + None + + + gui_areset_mode + Enable asynchronous clear / preset port + None + + + gui_enable_cke + Enable clock enable port + false + + + gui_hr_logic + Half Rate Logic + false + + + gui_ddio_with_delay + Input DDIO With Delay + false + + + gui_separate_io_clks + Separate input/output Clocks + false + + + SYS_INFO_DEVICE + SYS_INFO_DEVICE + A3CY050BB18AI6S + + + SYS_INFO_FAMILY + SYS_INFO_FAMILY + Agilex 3 + + + SYS_INFO_TRAIT_IOBANK_REVISION + SYS_INFO_TRAIT_IOBANK_REVISION + IO96B_REVB1 + + + EXT_DRIVER_PARAM + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + GENERATE_SDC_FILE + false + + + IP_MIGRATE_PORT_MAP_FILE + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 6 + + + AUTO_BOARD + Auto BOARD + default + + + + + + + board + Board + default + + + device + Device + A3CY050BB18AI6S + + + deviceFamily + Device family + Agilex 3 + + + deviceSpeedGrade + Device Speed Grade + 6 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element gpio_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file -- cgit v1.2.3-8-gadcc