diff options
Diffstat (limited to 'ml_module_agilex.qsf')
| -rw-r--r-- | ml_module_agilex.qsf | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/ml_module_agilex.qsf b/ml_module_agilex.qsf new file mode 100644 index 0000000..c326afb --- /dev/null +++ b/ml_module_agilex.qsf @@ -0,0 +1,69 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2026 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 26.1.0 Build 110 03/26/2026 SC Pro Edition +# Date created = 00:02:55 May 06, 2026 +# +# -------------------------------------------------------------------------- # +set_global_assignment -name TOP_LEVEL_ENTITY ml_module_agilex +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 26.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:02:55 MAY 06, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "26.1.0 Pro Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE A3CY050BB18AI6S +set_global_assignment -name FAMILY "Agilex 3" +set_global_assignment -name DEVICE_FILTER_PACKAGE VPBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 474 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name BOARD default +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[3] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[2] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[1] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_gpio[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_gpio[1] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_gpio -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_led[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_mdc -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rstn -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_mdio -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_intn -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[3] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[2] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_ctl -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_clk -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[1] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to clk_i -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_ctl -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_clk -entity ml_module_agilex +set_global_assignment -name VERILOG_FILE src/ml_module_agilex.v +set_global_assignment -name SDC_FILE ml_module_agilex.sdc +set_global_assignment -name IP_FILE ip/pll_io.ip +set_global_assignment -name IP_FILE ip/ddr_o.ip +set_global_assignment -name IP_FILE ip/ddr_i.ip +set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP |
