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+ReadMe file for ML Module FW Project
+
+UNF Summer Project sponsored by Private Island Networks Inc.
+
+See open source license file in same top level folder
+
+Project utilizes Altera Quartus Prime Pro and targets an Agilex 3 FPGA.
+
+Refer to project landing page for more information:  https://privateisland.tech/dev/ml-module-agilex
+
+Folders:
+
+src:  Verilog source code
+sim:  Simulation (see more below)
+ip:   IP files and related folders for both synth and simulation
+
+Build Folders (do not archive):
+dni
+output_files: this will eventually have the bit file for programming
+qdb
+
+Simulation Folders:
+data: data files read by the test bench
+lin: simulation project for Ubuntu Linux 24.04 (not currently supported in Questa)
+src: System Verilog test bench source
+wav: Simulation Wave files that can be invoked on sim command line using "do <file>"
+win: simulation project for Windows 
+
+Windows Simulation Folder:
+
+elab.do: run this the first time to compile Altera libraries (Fully compile in Quartus first)
+sim.do: run this each time you wish to start simulation
+ml_module.mpf: Questa project file.  Use this folder pane inside Questa to re-compile source files (and add them).
+
+To Simulate:
+
+# cd to project folder:
+> cd C:/Projects/fw_ml_module/sim/win
+> do elab.do
+> do ../wav/basic_wav.do
+> run 50 us
+
+
+
+