How to create an array of registers to capture Ethernet traffic in Verilog?
Sep 27, 2020 asked by anonymous
Question / Issue:
I want to create a special set of registers in the MAC layer for analysis and also capture in Reveal. Can you recommend a way to do this?
Date: Sept. 27, 2020
Author: Mind Chasers
localparam RX_MSG_Q_LEN = 'd32; reg [7:0] rx_message [0:RX_MSG_Q_LEN-1]; integer index; // Dedicated Message Queue (reset after each packet is received) always @(posedge clk or negedge rstn) if (!rstn) for (index=0; index<RX_MSG_Q_LEN; index = index + 1) rx_message[index] <= 8'h00; else if (rx_state == RX_ST_END) for (index=0; index<RX_MSG_Q_LEN; index = index + 1) rx_message[index] <= 8'h00; else if (!rx_k_m1 && rx_byte_cnt < RX_MSG_Q_LEN) begin rx_message[rx_byte_cnt] <= rx_data_m1; end