Overview
Meet our Betsy™ FPGA-based maker board for open source networking. Betsy is a multi-port GigE open source maker board designed for Private Island ® that utilizes the Altera Cyclone 10 LP. This awesome, general purpose FPGA provides 1 Gbps network connectivity utilizing DDR general purpose I/O (GPIO) implemented as RGMII.
This specification is for the V0.2 board, which is under development. The figure below shows the initial Betsy prototye (V0.1) on the lab bench. The dongle next to the board is an FTDI mini module configured as a JTAG debugger and programmer. Betsy is shown with an optional GigE (third port) daughter boad. A GPIO Expansiion board is also available with other daughter boards planned.
A block diagram of the V0.2 board is provided below.
FPGA: Cyclone 10 LP
- Device Part Number: 10CL025YU256C6G
- Process: 60 nm
- Core Voltage: 1.2V
- U256 package: 14 mm x 14 mm, 0.8 mm pitch
- Eight I/O banks:
- Row I/O banks 1, 2, 5, and 6, located on the left and right side of the device
- Column I/O banks 3, 4, 7, and 8, located on the top and bottom side of the device
Cyclone 10 LP Bank Assignments
| Bank | Sheet | Function |
|---|---|---|
| Bank 1 | 6 | Configuration |
| Bank 2 | 3 | RGMII 0 |
| Bank 3 | 3 | RGMII 0 |
| Bank 4 | 4 | RGMII 1 |
| Bank 5 | 4 | RGMII 1 |
| Bank 6 | 5 | RGMII 2 |
| Bank 7 | 5 | RGMII 2 |
| Bank 8 | 7 | Expansion |
Ethernet PHY
- Device Part Number: DP83867CSRGZ
V0.2 Change List
Listed below are the changes being made to the V0.2 board:
- Add FTDI FT2232H Circuit for JTAG Controller
- Which EPROM to add to hold Altera USB signature?
- Open issue: Add JTAG chain or potentially second JTAG port to daughter board connector
- Add Quad Buck Regulator circuit to support on-board power + barrel jack connector for external wall wart DC power
- Change daughter board form factor and connector location so daughter board stays within the base board outline.
- More expansion on Betsy for GPIO? Add another header? Add more test headers and GND posts?
- Review and resolve any critical Quartus warnings regarding jitter, timing, and I/O assignment.
- Review layout of PHY bypass capacitors and add any missing caps
- Add overlay boxes for S/N info
- 2-pin headers for each rail to monitor voltage
KiCad Project Cleanup List
Listed below are the various KiCad project issues:
- Reset all reference designators and create a new plan per sheet number
- One global flat netlist
- Why is there schematic sheet corruption with Linux?
- Remove all Altium artifacts
- Replace all power ports with KiCad native
- Solder mask bridging error (KiCad bug?)
- Add stackup information
- Create net classes for power, RGMII, LED, etc.
- Create design rules for RGMII trace lengths
- Resolve all schematic ERC errors & warnings
- Resolve all remaining PCB DRC errors & warnings
See the following KiCad forum posts for more information:
- There seems to be a bug related to: “solder mask aperture bridges items with different nets
- VCCA versus //VCCA. Where did the "//" come from and what does it mean?
Altera Cyclone 10 LP Related Acronyms
- ASx4: 4-bit Active Serial
- ALM: Adaptive Logic Modules
- ATX: Advanced Transmit (PLL). The ATX PLL is the transceiver channel’s primary transmit PLL.
- BER: Bit Error Ratio
- CTLE: Continuous Time Linear Equalization
- CDR: clock data recovery
- DFE:Decision Feedback Equalization
- CGB: Clock Generation Block
- CMU: Clock Multiplier Unit (PLL)
- CVP: Configuration Via Protocol
- DCM: Distributed Clock Mux
- DPA: Dynamic Phase Alignment
- fPLL: Fractional PLL
- FPP: Fast Passive Parallel configuration mode
- GCLK: Global Clock Network
- HPS: Hard Processor System
- HSSI: high-speed serial interface
- IOE: I/O Element
- JIC: JTAG Indirect File
- LAB: Logic Array Block, which consists of ALMs
- LPM: Library of Parameterized Modules
- LR: Long Reach (backplane)
- MLAB: Memory LAB
- OCT: On-chip Termination
- OpenCL: Open Computing Language
- PCLK:Periphery Clock Network
- PFD: Phase Frequency Detector
- PFL: Parallel Flash Loader
- PLL: Phase Lock Loop
- PIPE: PHY Interface For the PCI Express, SATA, USB 3.1, DisplayPort, and USB4 Architectures
- PreSICE: Precision Signal Integrity Calibration Engine
- SERDES: serializer / deserializer
- SCLK: Section Clock
- SFL: Serial Flash Loader
- SR: Short Reach (chip-to-chip)
- RCLK: Regional Clock Network
- SCLK: Section Clock
- TRS: Transceiver Reset Sequencer
- TREs: Transceiver Reset Endpoints
- VCCPT: Pre-Driver Voltage
